Microprocessor decoder frequency hopping spread spectrum communications receiver

• US 20040001532A1
• Filed: 06/26/2002
• Published: 01/01/2004
• Est. Priority Date: 06/26/2002
• Status: Active Grant

• Current Assignee: Elster Electricity LLC (Honeywell International Inc.)
• Original Assignee: Elster Electricity LLC (Honeywell International Inc.)
• Inventors: Hodges, Eugene W., Hemminger, Rodney C., Mason, Robert T. Jr., Brian, Brent R.
• Granted Patent: US 7,020,178 B2
• Time in Patent Office: Days
• US Class Current: 375/136
• CPC Class Codes: H04B 1/7156 Arrangements for sequence synchronisation
• CPC Class Codes: H04B 2001/71563 Acquisition

Abstract

The present invention is directed to a frequency hopping spread spectrum transceiver. The transceiver includes a microcontroller; a transmitter having a voltage controlled oscillator, a direct digital synthesizer, and a power amplifier; and a receiver having an amplifier, a mixer, an IF amplifier, a demodulator, and a data slicer. When transmitting, the transmitter sends a preamble that allows the receiving device to detect the signal and lock to it to receive the data. When receiving, the receiver first scans all channels and sorts them based on a Received Signal Strength Indicator (RSSI) and then attempts to lock to the channel with the strongest RSSI value by first sampling the received signal to verify the preamble, then synchronizing to the bit edges of the received signal, then detecting the start of a Start Frame Delimiter (SFD), decoding bits to verify a valid SFD and then sampling data bits to receive the data.

Claims

1. In a frequency hopping spread spectrum receiver, a method of validating a transmitted signal, comprising:

scanning a predetermined list of channels;

checking a received signal strength indicator signal for each scanned channel;

detecting a carrier signal on a selected channel;

locking to said selected channel; and

sampling for a start frame delimiter on said selected channel.

2. The method of claim 1, wherein said receiving said received signal strength indicator signal further comprises:

converting said received signal strength indicator signal to a digital value representative of said received signal strength indicator signal; and

storing said digital value in a received signal strength indicator list.

3. The method of claim 1, wherein said detecting said carrier signal further comprises:

searching a list of stored digital values representative of the received signal strength indicator signal for each scanned channel;

determining a largest non-zero value in said list of stored digital values;

setting said receiver to a first channel in accordance with said largest non-zero value; and

testing a PLL lock indicator until a lock is established.

4. The method as recited in claim 3, further comprising:

starting a timer;

sampling a signal on said first channel for a predetermined period of time to obtain a predetermined number of samples; and

correlating said predetermined number of samples with ideal bit patterns to determine a number of correlation errors.

5. The method as recited in claim 4, further comprising:

determining if said number of correlation errors is within a predetermined tolerance; and

determining a time offset based on said correlating of said predetermined number of samples with said ideal bit patterns.

6. The method as recited in claim 4, wherein said predetermined period of time is 2 bit times and wherein said predetermined number of samples is 32.

7. The method as recited in claim 4, wherein said correlating said predetermined number of samples with said ideal bit patterns comprises:

dividing said predetermined number of samples into two sets;

performing an exclusive OR operation on said two sets with said ideal bit patterns;

determining a number of ones as a result of the exclusive OR operation, said number of ones being indicative of a number of errors; and

determining the number of rotations needed to achieve the ideal bit pattern with the fewest errors, said of said rotations being generated by rotating 0xF00F.

8. The method as recited in claim 4, further comprising:

resampling said signal on said first channel for said predetermined period of time to obtain a predetermined number of second samples; and

correlating said predetermined number of second samples with said predetermined number of samples to determine a second number of correlation errors.

9. The method as recited in claim 1, wherein said locking to said selected channel comprises:

setting a timer;

recording samples on said channel;

comparing said samples to ideal preamble patterns; and

correlating errors between said samples and said preamble patterns.

10. The method as recited in claim 9, further comprising:

adjusting said timer to a down edge of bits within said samples; and

determining if a number of correlation errors is within a predetermined tolerance.

11. The method as recited in claim 1, wherein said sampling for said start frame delimiter on said selected channel comprises:

sampling each half bit of each bit received by the receiver;

voting the total number of samples to determine if each bit is a one or a zero; and

comparing the bits with a predetermined start frame delimiter pattern.

12. The method as recited in claim 11, wherein each bit is Manchester Encoded.

13. An asynchronous frequency hopping spread spectrum receiver, comprising:

an integrated circuit transceiver providing a PLL lock signal and a received signal strength indicator signal; and

a microcontroller that receives said PLL lock signal and said received signal strength indicator signal,

wherein said microcontroller converts said received signal strength indicator signal to a digital value representative of said received signal strength indicator signal and stores said digital value in a received signal strength indicator list, and

wherein said microcontroller sets said transceiver to a channel in accordance with a largest digital value in said received signal strength indicator list and tests said PLL lock signal until a lock is established.

14. The receiver of claim 13, wherein said microcontroller samples a signal on said channel for a predetermined period of time to obtain a predetermined number of samples and correlates said predetermined number of samples with ideal bit patterns to determine a number of correlation errors.

15. The receiver as recited in claim 14, wherein said microcontroller determines if said number of correlation errors is within a predetermined tolerance;

and determines a time offset based on said correlating of said second predetermined number of samples with said ideal bit patterns.

16. The receiver as recited in claim 14, wherein said microcontroller resamples said signal on said channel for said predetermined period of time to obtain a predetermined number of second samples and correlates said predetermined number of second samples with said predetermined number of samples to determine a second number of correlation errors.

17. The receiver as recited in claim 13, wherein said microcontroller locks to said selected channel by recording samples on said channel and correlating errors between said samples and preamble patterns.

18. The receiver as recited in claim 13, wherein said microcontroller samples said channel for a start frame delimiter by sampling each half bit of each bit received by the receiver and voting the total number of samples to determine if each bit is a one or a zero, and then comparing the bits with a predetermined start frame delimiter pattern.

19. A method of synchronizing a frequency hopping spread spectrum receiver with a transmitter, comprising:

searching a predetermined list of channels for a channel having a valid preamble;

refining bit timing in order to determine center of a bit; and

sampling for a start frame delimiter indicative of a beginning of a data frame on said channel.

20. The method as recited in claim 19, wherein searching said predetermined list of channels comprises:

receiving a received signal strength indicator signal for each scanned channel;

converting said received signal strength indicator signal to a digital value representative of said received signal strength indicator signal; and

storing said digital value in a received signal strength indicator list.

21. The method of claim 20, further comprising:

determining a largest non-zero value in said list of stored digital values;

setting said receiver to a first channel in accordance with said largest non-zero value; and

testing a PLL lock indicator until a lock is established;

sampling a signal on said first channel for a predetermined period of time to obtain a predetermined number of samples; and

correlating said predetermined number of samples with ideal bit patterns to determine a number of correlation errors.

22. The method as recited in claim 21, further comprising:

determining if said number of correlation errors is within a predetermined tolerance; and

determining a time offset based on said correlating of said predetermined number of samples with said ideal bit patterns.

23. The method as recited in claim 19, wherein said refining bit timing in order to determine center of a bit comprises:

recording samples on said channel;

comparing said samples to ideal preamble patterns;

correlating errors between said samples and said preamble patterns;

adjusting a timer to a down edge of bits within said samples; and

determining if a number of correlation errors is within a predetermined tolerance.

24. The method as recited in claim 19, wherein said sampling for said start frame delimiter on said channel comprises:

sampling each half bit of each bit received by the receiver;

voting the total number of samples to determine if each bit is a one or a zero; and

comparing the bits with a predetermined start frame delimiter pattern.