Organic ferroelectric memory cells

• US 20040002176A1
• Filed: 06/28/2002
• Published: 01/01/2004
• Est. Priority Date: 06/28/2002
• Status: Active Grant

• Current Assignee: Palo Alto Research Center, Inc. (Xerox Holdings Corp.)
• Original Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Inventors: Xu, Baomin
• Granted Patent: US 6,812,509 B2
• Time in Patent Office: Days
• US Class Current: 438/40
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors

Abstract

This invention proposes to make memory using organic materials. The basic structure of the memory cell is a field effect organic transistor using a ferroelectric thin film polymer as gate dielectric. By controlling the gate voltage to polarize the thin film ferroelectric polymer polarized in either an “up” or “down” state, the source-drain current can be controlled between two different values under the same source-drain voltage. The source-drain current thus can be used to represent either a “0” or “1” state. The organic thin film transistor can be made from poly(phenylenes), thiophene oligomers, pentacene, polythiophene, perfluoro copper phthalocyanine or other organic thin films. The ferroelectric thin film can be poly(vinylidene fluoride) (PVDF), poly(vinyldiene-trifluoroethylene) (P(VDF-TrFE)) copolymers, odd-numbered nylons, cyanopolymers, polyureas, or other ferroelectric thin films. As the deposition of these organic thin films can be done at temperatures below 200° C., the memory cell can be made on many kinds of substrates including plastics.

Claims

1. ) A memory cell comprising:

a) an organic semiconductor having two opposed surfaces;

b) two spaced apart electrodes in contact with one surface of the organic semiconductor, wherein the distance there between is a channel length and the portion of the organic semiconductor there between is defined as a channel region;

c) a ferroelectric polymer having a dielectric constant and two opposed surfaces wherein one surface is in contact with one surface of the organic semiconductor for at least a portion of the channel region; and

d) a gate electrode in contact with one surface of the ferroelectric polymer for at least a portion of the channel region.

2. ) The memory cell of claim 1 further comprising a substrate so constructed and arranged to provide support for the memory cell.

3. ) The memory cell of claim 2 wherein the substrate is at least partially adjacent to the gate electrode.

4. ) The memory cell of claim 2 wherein the substrate is at least partially adjacent to the organic semiconductor.

5. ) The memory cell of claim 2 wherein the substrate comprises a flexible substrate.

6. ) The memory cell of claim 2 wherein the substrate comprises a rigid substrate.

7. ) The memory cell of claim 2 wherein the substrate is at least partially conductive.

8. ) The memory cell of claim 7 wherein the substrate further comprises an insulative portion on a surface of the substrate.

9. ) The memory cell of claim 7 wherein the substrate comprises a metal.

10. ) The memory cell of claim 7 wherein the substrate comprises a semiconductor.

11. ) The memory cell of claim 2 wherein the substrate comprises a plastic.

12. ) The memory cell of claim 1 wherein the organic semiconductor has a thickness of at least 5 nm.

13. ) The memory cell of claim 12 wherein the organic semiconductor has a thickness of at least 50 nm.

14. ) The memory cell of claim 12 wherein the organic semiconductor has a thickness of approximately 100 nm.

15. ) The memory cell of claim 1 wherein the organic semiconductor has a field-effect mobility of at least 10⁻

5 cm²V<sup>−

1</sup>s^{31 1}.

16. ) The memory cell of claim 1 wherein the organic semiconductor has a field-effect mobility of at least 10⁻

3 cm²V<sup>−

1</sup>S<sup>−

1</sup>.

17. ) The memory cell of claim 1 wherein the ferroelectric polymer has a thickness of at least 5 nm.

18. ) The memory cell of claim 17 wherein the ferroelectric polymer has a thickness of at least 50 nm.

19. ) The memory cell of claim 17 wherein the ferroelectric polymer has a thickness of approximately 100 nm.

20. ) The memory cell of claim 1 wherein the ferroelectric polymer has a remnant polarization of at least 0.1 μ

C/cm².

21. ) The memory cell of claim 1 wherein the ferroelectric polymer has a remnant polarization of at least 0.5 μ

C/cm².

22. ) The memory cell of claim 1 wherein the gate electrode comprises a conductive material.

23. ) The memory cell of claim 22 wherein the gate electrode comprises a metal.

24. ) The memory cell of claim 22 wherein the gate electrode comprises a conductive oxide.

25. ) The memory cell of claim 22 wherein the gate electrode comprises a conductive polymer.

26. ) The memory cell of claim 1 wherein the two spaced apart electrodes comprise a conductive material.

27. ) The memory cell of claim 26 wherein the two spaced apart electrodes comprise a metal.

28. ) The memory cell of claim 26 wherein the two spaced apart electrodes comprise a conductive oxide.

29. ) The memory cell of claim 26 wherein the two spaced apart electrodes comprise a conductive polymer.

30. ) The memory cell of claim 1 further comprising an organic dielectric interposed between the ferroelectric polymer and the organic semiconductor.

31. ) The memory cell of claim 30 wherein the organic dielectric has a dielectric constant at least the same as the dielectric constant of the ferroelectric polymer.

32. ) The memory cell of claim 30 wherein the memory cell further comprises a floating gate electrode interposed between the ferroelectric polymer and the organic dielectric.

33. ) The memory cell of claim 32 wherein the floating gate electrode comprises a conductive material.

34. ) The memory cell of claim 33 wherein the floating gate electrode comprises a metal.

35. ) The memory cell of claim 33 wherein the floating gate electrode comprises a conductive oxide.

36. ) The memory cell of claim 33 wherein the floating gate electrode comprises a conductive polymer.