Productivity enhancing thermal sprayed yttria-containing coating for plasma reactor

• US 20040002221A1
• Filed: 06/27/2002
• Published: 01/01/2004
• Est. Priority Date: 06/27/2002
• Status: Active Grant

• Current Assignee: Lam Research Corporation
• Original Assignee: Lam Research Corporation
• Inventors: OʼDonnell, Robert J., Daugherty, John E.
• Granted Patent: US 7,311,797 B2
• Time in Patent Office: Days
• US Class Current: 438/710
• CPC Class Codes: C23C 16/4404 Coatings or surface treatment on the inside of the reaction chamber or on parts thereof
• CPC Class Codes: H01J 37/32467 Material
• CPC Class Codes: H01J 37/32477 characterised by the means for protecting vessels or internal parts, e.g. coatings
• CPC Class Codes: H01J 37/3255 Material

Abstract

Components of semiconductor processing apparatus comprise thermal sprayed yttria-containing coatings that provide erosion, corrosion and/or corrosion-erosion resistance in plasma atmospheres. The coatings can protect substrates from physical and/or chemical attack.

Claims

1. A component of a semiconductor processing apparatus, comprising:

a substrate including a surface; and

a thermal sprayed coating consisting essentially of yttria disposed over the surface, the coating including an outermost surface of the component.

2. The component of claim 1, wherein the coating is directly on the surface of the substrate without an intermediate layer of another material disposed between the coating and the surface of the substrate.

3. The component of claim 1, wherein the surface of the substrate is made of a material selected from the group consisting of anodized aluminum, alumina and quartz.

4. The component of claim 1, which is a chamber wall.

5. The component of claim 1, which is at least one component selected from the group consisting of a chamber wall, a chamber liner, a gas distribution plate, a gas ring, a pedestal, a dielectric window, an electrostatic chuck and a plasma focus ring.

6. The component of claim 1, wherein the coating has a thickness of from about 0.001 inch to about 0.1 inch.

7. The component of claim 1, further comprising at least one intermediate layer between the surface of the substrate and the coating.

8. The component of claim 1, wherein the coating has an arithmetic mean surface roughness (Ra) effective to promote adhesion of polymer deposits on the coating.

9. The component of claim 8, wherein the coating has an arithmetic mean surface roughness (Ra) from about 120 to about 250 micro-inch.

10. A chamber wall of a semiconductor processing apparatus, comprising:

an anodized aluminum substrate including a surface; and

a thermal sprayed coating consisting essentially of yttria disposed directly on the surface, the coating including an outermost surface of the component.

11. The chamber wall of claim 10, wherein the coating has an arithmetic mean surface roughness (Ra) that promotes adhesion of polymer deposits.

12. A plasma etch reactor, comprising:

at least one component including;

a substrate including a surface; and

a thermal sprayed coating consisting essentially of yttria disposed over the surface, the coating including an outermost surface of the component.

13. The plasma etch reactor of claim 12, wherein the surface of the substrate is anodized aluminum, and the coating is directly on the surface of the substrate without an intermediate layer of another material disposed between the coating and the surface of the substrate.

14. The plasma etch reactor of claim 13, wherein the component is a chamber wall and the plasma etch reactor includes a plasma generating source which inductively couples radio frequency energy into the reactor.

15. The plasma etch reactor of claim 12, wherein the coating has an arithmetic mean surface roughness (Ra) effective to promote adhesion of polymer deposits on the coating.

16. A process of manufacturing a component of a semiconductor processing apparatus, comprising applying a coating consisting essentially of yttria over a surface of a substrate by thermal spraying, the coating comprising an outermost surface of the component.

17. The process of claim 16, wherein the coating is applied directly on the surface of the substrate.

18. The process of claim 16, wherein the surface of the substrate is made of a material selected from the group consisting of anodized aluminum, alumina and quartz.

19. The process of claim 16, wherein the coating is formed to have an arithmetic mean surface roughness (Ra) effective to promote adhesion of polymer deposits.

20. A process of etching a semiconductor substrate, comprising:

placing a semiconductor substrate in a chamber of a plasma etch reactor, the plasma etch reactor comprising at least one component including a substrate having a surface and a thermal sprayed coating consisting essentially of yttria disposed over the surface, the coating including an outermost surface of the component;

introducing a process gas into the chamber;

generating a plasma from the process gas; and

etching the semiconductor substrate with the plasma,

wherein the coating is exposed to the plasma during the etching.

21. The process of claim 20, wherein the plasma is generated by inductively coupling radio frequency energy into the chamber.

22. The process of claim 20, wherein the semiconductor substrate comprises at least one silicon-containing material selected from the group consisting of single-crystal silicon, polycrystalline silicon, amorphous silicon, silicon nitride, silicon oxynitride, silicides, silicon dioxide, low-k materials and high-k materials.

23. The process of claim 20, wherein the semiconductor substrate comprises at least one metal-containing material selected from the group consisting of aluminum, aluminum alloys, tungsten, tungsten alloys, titanium, titanium alloys, tantalum, tantalum alloys, platinum, platinum alloys, ruthenium, ruthenium alloys, chrome, chrome alloys, iron, iron alloys, nickel, nickel alloys, cobalt, cobalt alloys, molybdenum, molybdenum alloys, silicides of titanium, tungsten, chrome, cobalt and/or molybdenum, ferroelectric materials and GMR materials.

24. The process of claim 20, wherein the coating has an arithmetic mean surface roughness (Ra) that promotes adhesion of polymer deposits on the coating during the etching.

25. A process of reducing contamination of a semiconductor wafer by erosion of a component in a chamber of a plasma etch reactor during etching of the semiconductor wafer in the plasma etch reactor, comprising:

placing a semiconductor wafer in a chamber of a plasma etch reactor, the plasma etch reactor comprising at least one component including a substrate comprised of a material and having a surface and a thermal sprayed coating consisting essentially of yttria disposed over the surface, the coating including an outermost surface of the component;

introducing a process gas into the chamber, the process gas being erosive with respect to the substrate material;

generating a plasma from the process gas; and

etching the semiconductor wafer with the plasma while exposing the coating to the plasma,

wherein the coating minimizes contamination of the semiconductor wafer by the substrate material and yttria during the etching.

26. The process of claim 25, wherein the substrate comprises aluminum or alloy thereof.

27. The process of claim 25, wherein the level of contamination of the semiconductor wafer by yttria is less than 10¹⁰ atoms/cm².

28. The process of claim 25, wherein the surface of the component is anodized aluminum, and the coating is directly on the anodized aluminum.

29. The process of claim 25, wherein the semiconductor wafer comprises at least one silicon-containing material and the process gas comprises fluorine.

30. The process of claim 29, wherein the silicon-containing material is selected from the group consisting of single-crystal silicon, polycrystalline silicon, amorphous silicon, silicon nitride, silicon oxynitride, silicides, silicon dioxide, low-k materials and high-k materials.

31. The process of claim 25, wherein the semiconductor wafer comprises at least one metal-containing material and the process gas comprises BCl₃.

32. The process of claim 31, wherein the metal-containing material is selected from the group consisting of aluminum, aluminum alloys, tungsten, tungsten alloys, titanium, titanium alloys, tantalum, tantalum alloys, platinum, platinum alloys, ruthenium, ruthenium alloys, chrome, chrome alloys, iron, iron alloys, nickel, nickel alloys, cobalt, cobalt alloys, molybdenum, molybdenum alloys, silicides of titanium, tungsten, chrome, cobalt and/or molybdenum, ferroelectric materials and GMR materials.

33. The process of claim 25, wherein the semiconductor wafer comprises silicon and the process gas comprises bromine.

34. The process of claim 25, wherein the process gas comprises BCl₃ and the coating is not eroded by the plasma during etching.