SCAN TEST METHOD FOR PROVIDING REAL TIME IDENTIFICATION OF FAILING TEST PATTERNS AND TEST BIST CONTROLLER FOR USE THEREWITH
First Claim
1. A method of scan testing an integrated circuit to provide real time identification of a block of test patterns having at least one failing test pattern, comprising:
- performing a number of test operations and storing a test response signature corresponding to each block of test patterns into a signature register;
replacing the test response signature in said signature register with a test block expected signature;
identifying said block as a failing test block when said test response signature is different from said test block expected signature; and
repeating the preceding steps until the test is complete.
5 Assignments
0 Petitions
Accused Products
Abstract
A method of scan testing an integrated circuit to provide real time identification of a block of test patterns having at least one failing test pattern comprises performing a number of test operations and storing a test response signature corresponding to each block of test patterns into a signature register; replacing the test response signature in the signature register with a test block expected signature; identifying the block as a failing test block when the test response signature is different from the test block expected signature; and repeating preceding steps until the test is complete.
50 Citations
70 Claims
-
1. A method of scan testing an integrated circuit to provide real time identification of a block of test patterns having at least one failing test pattern, comprising:
-
performing a number of test operations and storing a test response signature corresponding to each block of test patterns into a signature register;
replacing the test response signature in said signature register with a test block expected signature;
identifying said block as a failing test block when said test response signature is different from said test block expected signature; and
repeating the preceding steps until the test is complete. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36)
-
-
37. A method of scan testing an integrated circuit to provide real time identification of a block of test patterns having at least one failing test pattern, comprising:
for each of one or more blocks of core test patterns for each core under test;
processing each of said core test patterns including loading the test pattern into scannable memory element scan chains in said core at a respective core clock rate, capturing the response of the circuit to the core test pattern, unloading the test response from the memory elements, and compressing the test response into a core test response signature register;
concurrently with said processing, loading a test block expected signature into a core expected signature register at a common test clock rate;
upon completion of processing of each block of test patterns, replacing the test response signature in said test response signature register with said test block expected signature; and
identifying a block of test patterns as a failing test block when said test response signature is different from said test block expected signature. - View Dependent Claims (38, 39, 40, 41)
-
42. A test controller for use in self-testing of an integrated circuit under control of a first clock and providing real time identification of blocks of test patterns having at least one failing test pattern, the controller having a test response signature register for storing a compressed test response of the circuit to a block of test patterns, the improvement comprising:
-
an expected signature register having a serial input and a serial output, and a control circuit for controlling loading of an expected signature into said expected signature register under control of a test clock and for replacing the contents of the test response signature register with the contents of said expected signature register. - View Dependent Claims (43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58)
-
-
59. A test controller for use in self-testing of an integrated circuit under control of a first clock and providing real time identification of failing test patterns, the controller having a test response signature register for storing a compressed test response of the circuit to a test patterns, comprising:
-
an expected signature register having a serial input, a serial output, and a bit length which is at least equal to the bit length of said test response signature register;
a pattern counter for counting test patterns which have been executed;
a control circuit for controlling loading of said expected signature register under control of a test clock and for replacing the contents of said test response signature register with the contents of said expected signature register, said control circuit having a bit counter for counting the number of bits loaded into said test expected signature register, said control circuit being responsive to a predetermined test pattern count of said pattern counter for replacing the contents of said test response signature with the contents of said expected signature register;
an asynchronous interface circuit for synchronizing shift operations of said expected signature register when shift operations are performed under control of a second clock; and
a serial input connected to said expected signature register serial input for loading an expected signature into said controller. - View Dependent Claims (60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70)
-
Specification