Efficient method and apparatus for low latency forward error correction
First Claim
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1. A method for generating low latency Forward Error Correction (FEC) comprising:
- receiving a bit stream;
entering the bit stream into a Linear Feedback Shift Register (LFSR), the LFSR generating parity bits from the received bit stream; and
coupling the bit stream and corresponding parity bits into segments.
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Abstract
A method and apparatus for low latency Forward Error Correction (FEC) is described. The low latency FEC can be implemented utilizing shift registers, at least one Linear Feedback Shift Register (LFSR), and a local reference table.
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Citations
35 Claims
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1. A method for generating low latency Forward Error Correction (FEC) comprising:
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receiving a bit stream;
entering the bit stream into a Linear Feedback Shift Register (LFSR), the LFSR generating parity bits from the received bit stream; and
coupling the bit stream and corresponding parity bits into segments. - View Dependent Claims (2, 3, 4, 5)
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6. A circuit for generating low latency Forward Error Correction (FEC) comprising:
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a linear feedback shift register (LFSR) to receive a bit stream;
a first shift register coupled with the LFSR to receive an output from the LFSR; and
a second shift register coupled with the first shift register to receive the output from the first shift register, and to combine the output with the corresponding bit stream. - View Dependent Claims (7, 8, 9, 10)
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11. A circuit for generating low latency Forward Error Correction (FEC) comprising:
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a linear feedback shift register (LFSR) to receive a bit stream;
a first shift register coupled with the LFSR to receive an output from the LFSR; and
a second shift register coupled with the LFSR to receive the output from the LFSR, and to combine the output with the corresponding bit stream. - View Dependent Claims (12, 13, 14, 15)
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16. A method for decoding low latency Forward Error Correction (FEC) comprising:
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receiving a bit stream;
parsing received parity bits from the bit stream;
entering the remaining bit stream into a linear feedback shift register (LFSR) to generate parity bits; and
comparing the received parity bits to the generated parity bits to detect any difference. - View Dependent Claims (17, 18, 19)
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20. A circuit for decoding low latency Forward Error Correction (FEC) comprising:
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a first shift register to receive a bit stream, including received parity bits;
a linear feedback shift register (LFSR) to receive the data stream without the parity bits, and to generate a parity for the bit stream; and
a first comparator circuit, coupled to the LFSR and the first shift register, to compare the received parity to the generated parity. - View Dependent Claims (21, 22, 23)
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24. A machine-readable medium having stored thereon data representing sequences of instructions which, when executed by a processor, cause the processor to perform operations comprising:
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receiving a bit stream;
entering the bit stream into a Linear Feedback Shift Register to generate parity bits; and
coupling the bit stream and their corresponding parity bits. - View Dependent Claims (25, 26, 27, 28)
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29. A machine-readable medium having stored thereon data representing sequences of instructions which, when executed by a processor, cause the processor to perform operations comprising:
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receiving a bit stream;
parsing received parity bits from the bit stream;
entering the remaining bit stream into a linear feedback shift register (LFSR) to generate parity bits; and
comparing the received parity bits to the generated parity bits to detect any difference. - View Dependent Claims (30, 31, 32)
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33. A computing appliance comprising:
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a storage medium including executable content;
a control logic, coupled with the storage medium to selectively access and execute the content to generate a low latency FEC in a linear feedback manner. - View Dependent Claims (34, 35)
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Specification