Efficient method and apparatus for low latency forward error correction

• US 20040003334A1
• Filed: 06/30/2002
• Published: 01/01/2004
• Est. Priority Date: 06/30/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Boyanapalli, Vipin S.
• Granted Patent: US 7,007,223 B2
• Time in Patent Office: Days
• US Class Current: 714/752
• CPC Class Codes: G11B 20/1833 by adding special lists or symbols to the coded information G11B20/1806, G11B20/1866 take precedence
• CPC Class Codes: H03M 13/37 Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0058 Block-coded modulation

Abstract

A method and apparatus for low latency Forward Error Correction (FEC) is described. The low latency FEC can be implemented utilizing shift registers, at least one Linear Feedback Shift Register (LFSR), and a local reference table.

Claims

1. A method for generating low latency Forward Error Correction (FEC) comprising:

receiving a bit stream;

entering the bit stream into a Linear Feedback Shift Register (LFSR), the LFSR generating parity bits from the received bit stream; and

coupling the bit stream and corresponding parity bits into segments.

2. The method of claim 1 further comprising a table of predetermined values corresponding to different parity values, said predetermined values corresponding to bits in the bit stream.

3. The method of claim 2 wherein the table of predetermined values is stored in a lookup table.

4. The method of claim 1 wherein the bit stream is partitioned in 10 bit segments.

5. The method of claim 4 wherein the parity values are 5 bit values.

6. A circuit for generating low latency Forward Error Correction (FEC) comprising:

a linear feedback shift register (LFSR) to receive a bit stream;

a first shift register coupled with the LFSR to receive an output from the LFSR; and

a second shift register coupled with the first shift register to receive the output from the first shift register, and to combine the output with the corresponding bit stream.

7. The circuit of claim 6 wherein the received bit stream is a 10 bit data stream.

8. The circuit of claim 7 wherein the first shift register is a 5 bit register.

9. The circuit of claim 8 wherein the second shift register is a 15 bit register.

10. The circuit of claim 9 wherein the combined data stream is a FEC 2/3 data stream.

11. A circuit for generating low latency Forward Error Correction (FEC) comprising:

a linear feedback shift register (LFSR) to receive a bit stream;

a first shift register coupled with the LFSR to receive an output from the LFSR; and

a second shift register coupled with the LFSR to receive the output from the LFSR, and to combine the output with the corresponding bit stream.

12. The circuit of claim 11 wherein the received bit stream is a 10 bit data stream.

13. The circuit of claim 12 wherein the first shift register is a 5 bit register.

14. The circuit of claim 13 wherein the second shift register is a 15 bit register.

15. The circuit of claim 14 wherein the combined data stream is a FEC 2/3 data stream.

16. A method for decoding low latency Forward Error Correction (FEC) comprising:

receiving a bit stream;

parsing received parity bits from the bit stream;

entering the remaining bit stream into a linear feedback shift register (LFSR) to generate parity bits; and

comparing the received parity bits to the generated parity bits to detect any difference.

17. The method of claim 16 wherein the detected difference is a determined value.

18. The method of claim 17 further comprising a table of predetermined values corresponding to different parity values, said predetermined values corresponding to bits in the bit stream.

19. The method of claim 18 wherein the determined value and the predetermined values are compared, and the corresponding bits in the bit stream are changed.

20. A circuit for decoding low latency Forward Error Correction (FEC) comprising:

a first shift register to receive a bit stream, including received parity bits;

a linear feedback shift register (LFSR) to receive the data stream without the parity bits, and to generate a parity for the bit stream; and

a first comparator circuit, coupled to the LFSR and the first shift register, to compare the received parity to the generated parity.

21. The circuit of claim 20 wherein the first comparator circuit is an exclusive OR circuit.

22. The circuit of claim 20 further comprising a table of predetermined values to correspond to different parity values, said predetermined values to correspond to bits in the bit stream.

23. The circuit of claim 22 further comprising a second comparator circuit to compare the output of the first comparator circuit with the table to determine which corresponding bits in the bit stream are to be changed.

24. A machine-readable medium having stored thereon data representing sequences of instructions which, when executed by a processor, cause the processor to perform operations comprising:

receiving a bit stream;

entering the bit stream into a Linear Feedback Shift Register to generate parity bits; and

coupling the bit stream and their corresponding parity bits.

25. The medium of claim 24 further comprising a table of predetermined values corresponding to different parity values, said predetermined values corresponding to bits in the bit stream.

26. The medium of claim 25 wherein the table of predetermined values is stored in a lookup table.

27. The medium of claim 24 wherein the bit stream is partitioned in 10 bit segments.

28. The medium of claim 27 wherein the parity values are 5 bit values.

29. A machine-readable medium having stored thereon data representing sequences of instructions which, when executed by a processor, cause the processor to perform operations comprising:

receiving a bit stream;

parsing received parity bits from the bit stream;

entering the remaining bit stream into a linear feedback shift register (LFSR) to generate parity bits; and

comparing the received parity bits to the generated parity bits to detect any difference.

30. The medium of claim 29 wherein the detected difference is a determined value.

31. The medium of claim 30 further comprising a table of predetermined values corresponding to different parity values, said predetermined values corresponding to bits in the bit stream.

32. The medium of claim 31 wherein the determined value and the predetermined values are compared, and the corresponding bits in the bit stream are changed.

33. A computing appliance comprising:

a storage medium including executable content;

a control logic, coupled with the storage medium to selectively access and execute the content to generate a low latency FEC in a linear feedback manner.

34. A computing system according to claim 33, further comprising an input port, to receive a bit stream from a network device.

35. A computing appliance according to claim 34 further comprising an output port, coupled to a network device, to send the Forward Error Corrected bit stream to the network device.