Test assembly including a test die for testing a semiconductor product die

• US 20040004216A1
• Filed: 12/11/2002
• Published: 01/08/2004
• Est. Priority Date: 01/15/1997
• Status: Active Grant

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Eldridge, Benjamin N., Khandros, Igor Y., Pedersen, David V., Whitten, Ralph G.
• Granted Patent: US 6,825,052 B2
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: G01R 1/07307 with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
• CPC Class Codes: G01R 1/07342 the body of the probe being at an angle other than perpendicular to test object, e.g. probe card
• CPC Class Codes: G01R 1/07371 using an intermediate card or back card with apertures through which the probes pass
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01076 : Osmium [Os]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H05K 3/20 : by affixing prefabricated conductor pattern H05K1/187, H05K3/046, H05K3/4658, H05K3/4682 takes precedence
• CPC Class Codes: H05K 3/3421 : Leaded components

Abstract

One embodiment of the present invention concerns a test assembly for testing product circuitry of a product die. In one embodiment, the test assembly includes at test die and an interconnection substrate for electrically coupling the test die to a host controller that communicates with the test die. The test die may be designed according to a design methodology that includes the step of concurrently designing test circuitry and a product circuitry in a unified design. The test circuitry can be designed to provide a high degree of fault coverage for the corresponding product circuitry generally without regard to the amount of silicon area that will be required by the test circuitry. The design methodology then partitions the unified design into the test die and the product die. The test die includes the test circuitry and the product die includes the product circuitry. The product and test die may then be fabricated on separate semiconductor wafers. By partitioning the product circuitry and test circuitry into separate die, embedded test circuitry can be either eliminated or minimized on the product die. This will tend to decrease the size of the product die and decrease the cost of manufacturing the product die while maintaining a high degree of test coverage of the product circuits within the product die. The test die can be used to test multiple product die on one or more wafers.

Claims

1. A test assembly for testing product circuitry of a product die, the test assembly comprising:

a test die having test circuitry for testing the product circuitry of the product die, the test circuitry generated by;

(i) concurrently designing the test circuitry and the product circuitry into a unified design, (ii) partitioning the test circuitry from the product circuitry, and (iii) fabricating the test circuitry into the test die; and

an interconnection substrate for electrically coupling the test die to a host controller that communicates with the test die.

2. The test assembly of claim 1, wherein the test die further comprises a plurality of pads coupled to the test circuitry.

3. The test assembly of claim 2, wherein the plurality of pads comprise:

bond pads; and

special contact pads for receiving spring contact elements.

4. The test assembly of claim 3, wherein the bond pads and special contact pads have different heights.

5. The test assembly of claim 1, further comprising contact elements to electrically couple the test circuitry and the product circuitry.

6. The test assembly of claim 5, wherein the contact elements have different heights.

7. The test assembly of claim 5, wherein the plurality of contact elements comprise spring contact elements.

8. The test assembly of claim 5, wherein the plurality of contact elements comprise contact balls.

9. The test assembly of claim 1, wherein the test circuitry is configured to test AC parametrics of the product circuitry.

10. The test assembly of claim 1, wherein the test circuitry is configured to test DC parametrics of the product circuitry.

11. The test assembly of claim 1, wherein the test circuitry is configured to program the product circuitry.

12. The test assembly of claim 1, wherein the test die is formed on a semiconductor wafer.

13. The test assembly of claim 1, wherein the test circuitry is configured to test product circuitry of more than one product die.

14. The test assembly of claim 1, further comprising a second test die electrically coupled to the interconnect substrate.

15. The test assembly of claim 14, wherein the second test die includes test circuitry for testing the product circuitry of the product die.

16. The test assembly of claim 15, wherein the second test die includes test circuitry for testing product circuitry of another product die.

17. The test assembly of claim 14, further comprising a third test die electrically coupled to, and communicating with, the first die and the second test die.

18. The test assembly of claim 17, wherein the third test die includes circuitry for performing a function that is commonly used by the first and second test die to test circuitry of the first and second product die.

19. A test assembly for testing product circuitry of a product die, the test assembly comprising:

a first test die having test circuitry for testing the product circuitry of the product die;

a second test die having test circuitry for testing the product circuitry of the product die; and

an interconnection substrate for electrically coupling the first test die and second test die to a host controller.

20. A test assembly for testing product circuitry of a plurality of product die, the test assembly comprising:

a test die having test circuitry for testing the product circuitry of the plurality product die; and

an interconnection substrate for electrically coupling the test die to a host controller that communicates with the test die.

21. The test assembly of claim 20, wherein the test die further comprises a plurality of pads coupled to the test circuitry.

22. The test assembly of claim 21, wherein the plurality of pads comprise:

bond pads; and

special contact pads for receiving spring contact elements.

23. The test assembly of claim 22, wherein the bond pads and special contact pads have different heights.

24. The test assembly of claim 21, further comprising contact elements coupled to the pads and for making electrically coupling the test circuitry and the product circuitry.

25. The test assembly of claim 24, wherein the contact elements have different heights.

26. The test assembly of claim 24, wherein the plurality of contact elements comprise spring contact elements.

27. The test assembly of claim 24, wherein the plurality of contact elements comprise contact balls.

28. The test assembly of claim 20, wherein the test circuitry is configured to test AC parametrics of the product circuitry of the plurality of product die.

29. The test assembly of claim 20, wherein the test circuitry is configured to test DC parametrics of the product circuitry of the plurality of product die.

30. The test assembly of claim 20, wherein the test circuitry is configured to program the product circuitry of the plurality of product die.

31. The test assembly of claim 20, wherein the test die is formed on a semiconductor wafer.

32. A test assembly comprising:

a first test die having test circuitry for testing product circuitry of a first product die;

a second test die having test circuitry for testing product circuitry of a second product die;

a third test die having circuitry for providing communicating test signals with the first and second test die; and

an interconnection substrate for electrically coupling the first, second, and third test die.

33. The test assembly of claim 32, wherein the third test die communicates with a host controller.

34. The test assembly of claim 33, wherein the third test die includes circuitry for performing a function that is commonly used by the first and second test die to test product circuitry of the first and second product die.

35. A test assembly for testing product circuitry of a product die, the test assembly comprising:

a test die having test circuitry for testing the product circuitry of the product die, the test circuitry generated by;

(i) concurrently designing the test circuitry and the product circuitry into a unified design, (ii) partitioning the test circuitry from the product circuitry, and (iii) fabricating the test circuitry into the test die;

a contactor having contact elements for electrically coupling signals from the test circuitry to the product circuitry; and

an interconnection substrate for electrically coupling the test die to the contactor.

36. The test assembly of claim 35, wherein the contactor comprises a cantilevered probe card.

37. The test assembly of claim 35, wherein the contactor comprises a membrane probe card.

38. The test assembly of claim 35, wherein the contactor comprises a COBRA-style probe card.

39. The test assembly of claim 35, wherein the interconnect substrate comprises an interposer and the contactor comprises:

a probe card electrically coupled to the interposer; and

a space transformer electrically coupled to the interposer.