Memory utilizing oxide-nitride nanolaminates

• US 20040004247A1
• Filed: 07/08/2002
• Published: 01/08/2004
• Est. Priority Date: 07/08/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Granted Patent: US 7,847,344 B2
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Structures, systems and methods for transistors utilizing oxide-nitride nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide-nitride nanolaminate layers to trap charge in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers.

Claims

1. A transistor, comprising:

a first source/drain region

a second source/drain region

a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator; and

wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers.

2. The transistor of claim 1, wherein the oxide-nitride nanolaminate layers include silicon nitride.

3. The transistor of claim 1, wherein the oxide-nitride nanolaminate layers include aluminum nitride.

4. The transistor of claim 1, wherein the oxide-nitride nanolaminate layers include gallium nitride.

5. The transistor of claim 1, wherein the oxide-nitride nanolaminate layers include gallium aluminum nitride.

6. The transistor of claim 1, wherein the oxide-nitride nanolaminate layers include tantalum aluminum nitride.

7. The transistor of claim 1, wherein the oxide-nitride nanolaminate layers include titanium silicon nitride.

8. The transistor of claim 1, wherein the oxide-nitride nanolaminate layers include titanium aluminum nitride.

9. The transistor of claim 1, wherein the oxide-nitride nanolaminate layers include tungsten aluminum nitride.

22. The vertical multistate cell of claim 6, wherein the number of charge levels trapped in the gate insulator adjacent the first source/drain region includes a trapped electron charge.

23. The vertical multistate cell of claim 6, wherein the gate insulator has a thickness of approximately 1-10 nanometers (nm).

10. A vertical multistate cell, comprising:

a vertical metal oxide semiconductor field effect transistor (MOSFET) extending outwardly from a substrate, the MOSFET having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator, wherein the gate insulator includes oxide-nitride nanolaminate layers adapted to trap charge in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers;

a sourceline coupled to the first source/drain region;

a transmission line coupled to the second source/drain region; and

wherein the MOSFET is a programmed MOSFET having one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2).

11. The vertical multistate cell of claim 10, wherein the oxide-nitride nanolaminate layers include silicon nitride.

12. The vertical multistate cell of claim 10, wherein the oxide-nitride nanolaminate layers include aluminum nitride.

13. The vertical multistate cell of claim 10, wherein the oxide-nitride nanolaminate layers include gallium nitride.

14. The vertical multistate cell of claim 10, wherein the oxide-nitride nanolaminate layers include gallium aluminum nitride.

15. The vertical multistate cell of claim 10, wherein the oxide-nitride nanolaminate layers include tantalum aluminum nitride.

16. The vertical multistate cell of claim 10, wherein the oxide-nitride nanolaminate layers include titanium silicon nitride.

17. The vertical multistate cell of claim 10, wherein the oxide-nitride nanolaminate layers include titanium aluminum nitride.

18. The vertical multistate cell of claim 10, wherein the oxide-nitride nanolaminate layers include tungsten aluminum nitride.

19. The vertical multistate cell of claim 10, wherein the first source/drain region of the MOSFET includes a source region and the second source/drain region of the MOSFET includes a drain region.

20. The vertical multistate cell of claim 19, wherein the second voltage threshold region (Vt2) in the channel is adjacent the source region, and wherein the first voltage threshold region (Vt1) in the channel is adjacent the drain region.

21. The multistate cell of claim 20, wherein the Vt2 has a higher voltage threshold than the Vt1.

47. The transistor array of claim 21, wherein the gate insulator of each transistor cell has a thickness of approximately 1-10 nanometers (nm).

48. The transistor array of claim 21, wherein the number of transistor cells extending from a substrate operate as equivalent to a transistor having a size equal to or than 1.0 lithographic feature squared (1F²).

24. A vertical multistate cell, comprising:

a vertical metal oxide semiconductor field effect transistor (MOSFET) extending outwardly from a substrate, the MOSFET having a source region, a drain region, a channel region between the source region and the drain region, and a gate separated from the channel region by a gate insulator wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers;

a wordline coupled to the gate;

a sourceline formed in a trench adjacent to the vertical MOSFET, wherein the source region is coupled to the sourceline;

a bit line coupled to the drain region; and

wherein the MOSFET is a programmed MOSFET having a number of charge levels trapped in the gate insulator adjacent to the source region such that the channel region has a first voltage threshold region (Vt1) adjacent to the drain region and a second voltage threshold region (Vt2) adjacent to the source region, the Vt2 having a greater voltage threshold than Vt1.

25. The vertical multistate cell of claim 24, wherein the oxide-nitride nanolaminate layers include silicon nitride.

26. The vertical multistate cell of claim 24, wherein the oxide-nitride nanolaminate layers include aluminum nitride.

27. The vertical multistate cell of claim 24, wherein the oxide-nitride nanolaminate layers include gallium nitride.

28. The vertical multistate cell of claim 24, wherein the oxide-nitride nanolaminate layers include gallium aluminum nitride.

29. The vertical multistate cell of claim 24, wherein the oxide-nitride nanolaminate layers include tantalum aluminum nitride.

30. The vertical multistate cell of claim 24, wherein the oxide-nitride nanolaminate layers include titanium silicon nitride.

31. The vertical multistate cell of claim 24, wherein the oxide-nitride nanolaminate layers include titanium aluminum nitride.

32. The vertical multistate cell of claim 24, wherein the oxide-nitride nanolaminate layers include tungsten aluminum nitride.

33. The vertical multistate cell of claim 24, wherein the oxide-nitride nanolaminate layers have atomic dimensions with precisely controlled interfaces and layer thickness formed by atomic layer deposition (ALD).

34. The vertical multistate cell of claim 24, wherein the gate insulator has a thickness of approximately 1-10 nanometers (nm).

35. A transistor array, comprising:

a number of transistor cells formed on a substrate, wherein each transistor cell includes a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator, and wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers;

a number of bit lines coupled to the second source/drain region of each transistor cell along rows of the transistor array;

a number of word lines coupled to the gate of each transistor cell along columns of the memory array;

a number of sourcelines, wherein the first source/drain region of each transistor cell is coupled to the number of sourcelines along rows of the transistor cells; and

wherein at least one of transistor cells is a programmed transistor having one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2).

36. The transistor array of claim 35, wherein the oxide-nitride nanolaminate layers include silicon nitride.

37. The transistor array of claim 35, wherein the oxide-nitride nanolaminate layers include aluminum nitride.

38. The transistor array of claim 35, wherein the oxide-nitride nanolaminate layers include gallium nitride.

39. The transistor array of claim 35, wherein the oxide-nitride nanolaminate layers include gallium aluminum nitride.

40. The transistor array of claim 35, wherein the oxide-nitride nanolaminate layers include tantalum aluminum nitride.

41. The transistor array of claim 35, wherein the oxide-nitride nanolaminate layers include titanium silicon nitride.

42. The transistor array of claim 35, wherein the oxide-nitride nanolaminate layers include titanium aluminum nitride.

43. The transistor array of claim 35, wherein the oxide-nitride nanolaminate layers include tungsten aluminum nitride.

44. The transistor array of claim 35, wherein the one of a number of charge levels trapped in the gate insulator includes a charge adjacent to the source of approximately 100 electrons.

45. The transistor array of claim 35, wherein the first source/drain region of the transistor cell includes a source region and the second source/drain region of the transistor cell includes a drain region.

46. The transistor array of claim 35, wherein the second voltage threshold region (Vt2) in the channel is adjacent the first source/drain region, and wherein the first voltage threshold region (Vt1) in the channel is adjacent the second source/drain region, and wherein Vt2 has a higher voltage threshold than the Vt1.

49. A memory array, comprising:

a memory array, wherein the memory array includes a number of vertical pillars formed in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein the number of vertical pillars serve as transistors including a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator in the trenches along rows of pillars, and wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers, wherein along columns of the pillars adjacent pillars include a transistor which operates as a multistate cell on one side of a trench and a transistor which operates as a reference cell having a programmed conductivity state on the opposite side of the trench;

a number of bit lines coupled to the drain region of each transistor along rows of the memory array;

a number of word lines coupled to the gate of each transistor along columns of the memory array;

a number of sourcelines formed in a bottom of the trenches between rows of the pillars and coupled to the source regions of each transistor along rows of pillars, wherein along columns of the pillars the source region of each transistor in column adjacent pillars couple to the sourceline in a shared trench such that a multistate cell transistor and a reference cell transistor share a common sourceline;

a wordline address decoder coupled to the number of wordlines;

a bitline address decoder coupled to the number of bitlines;

a sense amplifier coupled to the number of bitlines; and

wherein at least one of multistate cell transistors is a programmed transistor having one of a number of charge levels trapped in the gate insulator adjacent to the source region such that the channel region of that transistor has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed transistor operates at reduced drain source current.

50. The memory array of claim 49, wherein the number of sourcelines formed in a bottom of the trenches between rows of the pillars include a doped region implanted in the bottom of the trench.

51. The memory array of claim 49, wherein the one of a number of charge levels trapped in the gate insulator includes a charge adjacent to the source region of approximately 100 electrons.

52. The memory array of claim 49, wherein the second voltage threshold region (Vt2) in the channel is adjacent the source region, and wherein the first voltage threshold region (Vt1) in the channel is adjacent the drain region, and wherein Vt2 has a higher voltage threshold than the Vt1.

53. The memory array of claim 49, wherein the gate insulator of each multistate cell transistor has a thickness of approximately 1-10 nanometers (nm).

54. The memory array of claim 49, wherein the oxide-nitride nanolaminate layers include silicon nitride.

55. The memory array of claim 49, wherein the oxide-nitride nanolaminate layers include aluminum nitride.

56. The memory array of claim 49, wherein the oxide-nitride nanolaminate layers include gallium nitride.

57. The memory array of claim 49, wherein the oxide-nitride nanolaminate layers include gallium aluminum nitride.

58. The memory array of claim 49, wherein the oxide-nitride nanolaminate layers include tantalum aluminum nitride.

59. The memory array of claim 49, wherein the oxide-nitride nanolaminate layers include titanium silicon nitride.

60. The memory array of claim 49, wherein the oxide-nitride nanolaminate layers include titanium aluminum nitride.

61. The memory array of claim 49, wherein the oxide-nitride nanolaminate layers include tungsten aluminum nitride.

62. The memory array of claim 49, wherein the wordline address decoder and the bitline address decoder each include conventionally fabricated MOSFET transistors having thin gate insulators formed of silicon dioxide (SiO₂).

63. The memory array of claim 49, wherein the sense amplifier includes conventionally fabricated MOSFET transistors having thin gate insulators formed of silicon dioxide (SiO₂).

64. A programmable logic array, comprising:

a plurality of input lines for receiving an input signal;

a plurality of output lines; and

one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to a received input signal, wherein each logic cell includes a transistor cell including;

a first source/drain region;

a second source/drain region;

a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator; and

wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers.

65. The programmable logic array of claim 64, wherein the oxide-nitride nanolaminate layers include silicon nitride.

66. The programmable logic array of claim 64, wherein the oxide-nitride nanolaminate layers include aluminum nitride.

67. The programmable logic array of claim 64, wherein the oxide-nitride nanolaminate layers include gallium nitride.

68. The programmable logic array of claim 64, wherein the oxide-nitride nanolaminate layers include gallium aluminum nitride.

69. The programmable logic array of claim 64, wherein the oxide-nitride nanolaminate layers include tantalum aluminum nitride.

70. The programmable logic array of claim 64, wherein the oxide-nitride nanolaminate layers include titanium silicon nitride.

71. The programmable logic array of claim 64, wherein the oxide-nitride nanolaminate layers include titanium aluminum nitride.

72. The programmable logic array of claim 64, wherein the oxide-nitride nanolaminate layers include tungsten aluminum nitride.

73. An electronic system, comprising:

a processor; and

a memory device coupled to the processor, wherein the memory device includes;

a memory array, wherein the memory array includes a number of vertical pillars formed in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein the number of vertical pillars serve as transistors including a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator in the trenches along rows of pillars, and wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers, wherein along columns of the pillars adjacent pillars include a transistor which operates as a multistate cell on one side of a trench and a transistor which operates as a reference cell having a programmed conductivity state on the opposite side of the trench;

a number of bit lines coupled to the drain region of each transistor along rows of the memory array;

a number of word lines coupled to the gate of each transistor along columns of the memory array;

a number of sourcelines formed in a bottom of the trenches between rows of the pillars and coupled to the source regions of each transistor along rows of pillars, wherein along columns of the pillars the source region of each transistor in column adjacent pillars couple to the sourceline in a shared trench such that a multistate cell transistor and a reference cell transistor share a common sourceline;

a wordline address decoder coupled to the number of wordlines;

a bitline address decoder coupled to the number of bitlines;

a sense amplifier coupled to the number of bitlines; and

wherein at least one of multistate cell transistors is a programmed transistor having one of a number of charge levels trapped in the gate insulator adjacent to the source region such that the channel region of that transistor has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed transistor operates at reduced drain source current.

74. The electronic system of claim 73, wherein the number of sourcelines formed in a bottom of the trenches between rows of the pillars include a doped region implanted in the bottom of the trench.

75. The electronic system of claim 73, wherein the one of a number of charge levels trapped in the gate insulator includes a charge adjacent to the source region of approximately 100 electrons.

76. The electronic system of claim 73, wherein the second voltage threshold region (Vt2) in the channel is adjacent the source region, and wherein the first voltage threshold region (Vt1) in the channel is adjacent the drain region, and wherein Vt2 has a higher voltage threshold than the Vt1.

77. The electronic system of claim 73, wherein the gate insulator of each transistor has a thickness of approximately 10 nanometers (nm).

78. The electronic system of claim 73, wherein the oxide-nitride nanolaminate layers include silicon nitride.

79. The electronic system of claim 73, wherein the oxide-nitride nanolaminate layers include aluminum nitride.

80. The electronic system of claim 73, wherein the oxide-nitride nanolaminate layers include gallium nitride.

81. The electronic system of claim 73, wherein the oxide-nitride nanolaminate layers include gallium aluminum nitride.

82. The electronic system of claim 73, wherein the oxide-nitride nanolaminate layers include tantalum aluminum nitride.

83. The electronic system of claim 73, wherein the oxide-nitride nanolaminate layers include titanium silicon nitride.

84. The electronic system of claim 73, wherein the oxide-nitride nanolaminate layers include titanium aluminum nitride.

85. The electronic system of claim 73, wherein the oxide-nitride nanolaminate layers include tungsten aluminum nitride.

86. The electronic system of claim 73, wherein each transistor operates as equivalent to a transistor having a size equal to or less than 1.0 lithographic feature squared (1F²).

87. The electronic system of claim 73, wherein, in a read operation, a sourceline for two column adjacent pillars sharing a trench is coupled to a ground potential, the drain regions of the column adjacent pillars sharing a trench are precharged to a fractional voltage of VDD, and the gate for each of the column adjacent pillars sharing a trench is addressed such that a conductivity state of a multistate cell transistor can be compared to a conductivity state of a reference cell transistor.

88. The electronic system of claim 73, wherein, in a write operation, a sourceline for two column adjacent pillars sharing a trench is biased to a voltage higher than VDD, one of the drain regions of the column adjacent pillars sharing a trench is coupled to a ground potential, and the gate for each of the column adjacent pillars sharing a trench is addressed with a wordline potential.

89. A method for operating a transistor array, comprising:

programming one or more transistors in the array in a reverse direction, wherein each transistor includes a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator, wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers, wherein the array includes a number of sourcelines coupled to the source regions of each transistor along rows in the array, and wherein the array includes a number of bitlines coupled to the drain region along rows in the array, and wherein programming the one or more transistors in the reverse direction includes;

applying a first voltage potential to a drain region of the transistor;

applying a second voltage potential to a source region of the transistor;

applying a gate potential to a gate of the transistor; and

wherein applying the first, second and gate potentials to the one or more transistors includes creating a hot electron injection into the gate insulator of the one or more transistors adjacent to the source region such that the one or more transistors become programmed transistors having one of a number of charge levels trapped in the gate insulator such that the programmed transistor operates at reduced drain source current in a forward direction.

90. The method of claim 89, wherein applying a first voltage potential to the drain region of the transistor includes grounding the drain region of the transistor.

91. The method of claim 90, wherein applying a second voltage potential to the source region includes applying a high voltage potential (VDD) to a sourceline coupled thereto.

92. The method of claim 91, wherein applying a gate potential to the gate of the transistor includes applying a gate potential to the gate in order to create a conduction channel between the source and drain regions of the transistor.

93. The method of claim 89, wherein the method further includes reading one or more transistors in the array by operating an addressed transistor in a forward direction, wherein operating the transistor in the forward direction includes:

grounding the source region for the addressed transistor;

precharging the drain region for the addressed transistor to a fractional voltage of VDD; and

applying a gate potential of approximately 1.0 Volt to the gate for the addressed transistor such that a conductivity state of the addressed transistor can be compared to a conductivity state of a reference cell.

94. The method of claim 89, wherein in creating a hot electron injection into the gate insulator of the one or more transistors adjacent to the source region includes creating a first threshold voltage region (Vt1) adjacent to the drain region and creating a second threshold voltage region (Vt2) adjacent to the source region.

95. A method for multistate memory, comprising:

writing to one or more vertical MOSFETs arranged in rows and columns extending outwardly from a substrate and separated by trenches in a DRAM array in a reverse direction, wherein each MOSFET in the DRAM array includes a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator in the trenches, wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers, wherein the DRAM array includes a number of sourcelines formed in a bottom of the trenches between rows of the vertical MOSFETs and coupled to the source regions of each transistor along rows the vertical MOSFETs, wherein along columns of the vertical MOSFETs the source region of each column adjacent vertical MOSFET couple to the sourceline in a shared trench, and wherein the DRAM array includes a number of bitlines coupled to the drain region along rows in the DRAM array, and wherein programming the one or more vertical MOSFETs in the reverse direction includes;

biasing a sourceline for two column adjacent vertical MOSFETs sharing a trench to a voltage higher than VDD;

grounding a bitline coupled to one of the drain regions of the two column adjacent vertical MOSFETs in the vertical MOSFET to be programmed

applying a gate potential to the gate for each of the two column adjacent vertical MOSFETs to create a hot electron injection into the gate insulator of the vertical MOSFET to be programmed adjacent to the source region such that an addressed MOSFETs becomes a programmed MOSFET and will operate at reduced drain source current in a forward direction;

reading one or more vertical MOSFETs in the DRAM array in a forward direction, wherein reading the one or more MOSFETs in the forward direction includes;

grounding a sourceline for two column adjacent vertical MOSFETs sharing a trench;

precharging the drain regions of the two column adjacent vertical MOSFETs sharing a trench to a fractional voltage of VDD; and

applying a gate potential of approximately 1.0 Volt to the gate for each of the two column adjacent vertical MOSFETs sharing a trench such that a conductivity state of an addressed vertical MOSFET can be compared to a conductivity state of a reference cell.

96. The method of claim 95, wherein creating a hot electron injection into the gate insulator of the addressed MOSFET adjacent to the source region includes creating a first threshold voltage region (Vt1) adjacent to the drain region and creating a second threshold voltage region (Vt2) adjacent to the source region, wherein Vt2 is greater that Vt1.

97. The method of claim 95, wherein reading one or more vertical MOSFETs in the DRAM array in a forward direction includes using a sense amplifier to detect whether an addressed vertical MOSFET is a programmed vertical MOSFET, wherein a programmed vertical MOSFET will not conduct, and wherein an unprogrammed vertical MOSFET addressed over approximately 10 ns will conduct a current of approximately 12.5 μ

A such that the method includes detecting an integrated drain current having a charge of 800,000 electrons using the sense amplifier.

98. The method of claim 95, wherein in creating a hot electron injection into the gate insulator of an addressed vertical MOSFET includes changing a threshold voltage for the vertical MOSFET by approximately 0.5 Volts.

99. The method of claim 95, wherein creating a hot electron injection into the gate insulator of the addressed vertical MOSFET includes trapping a stored charge in the gate insulator of the addressed vertical MOSFET of approximately 10¹² electrons/cm².

100. The method of claim 95, wherein creating a hot electron injection into the gate insulator of the addressed vertical MOSFET includes trapping a stored charge in the gate insulator of the addressed vertical MOSFET of approximately 100 electrons.

101. The method of claim 95, wherein the method further includes using the vertical MOSFET as active device with gain, and wherein reading a programmed vertical MOSFET includes providing an amplification of a stored charge in the gate insulator from 100 to 800,000 electrons over a read address period of approximately 10 ns.

102. A method for forming a transistor, comprising:

forming a first source/drain region, a second source/drain region, and a channel region therebetween in a substrate;

forming a gate insulator opposing the channel region, wherein forming the gate insulator includes forming oxide-nitride nanolaminate layers which trap charge in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers; and

forming a gate opposing the gate insulator.

103. The method of claim 102, wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of silicon nitride.

104. The method of claim 102, wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of aluminum nitride.

105. The method of claim 102, wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of gallium nitride.

106. The method of claim 102, wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of gallium aluminum nitride.

107. The method of claim 102, wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of tantalum aluminum nitride.

108. The method of claim 102, wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of titanium silicon nitride.

109. The method of claim 102, wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of titanium aluminum nitride.

110. The method of claim 102, wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of tungsten aluminum nitride.

111. A method for forming a multistate memory array, comprising:

forming a number of vertical pillars in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein the number of vertical pillars serve as transistors including a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator in the trenches along rows of pillars, wherein along columns of the pillars adjacent pillars include a transistor which operates as a multistate cell on one side of a trench and a transistor which operates as a reference cell having a programmed conductivity state on the opposite side of the trench, and wherein forming the gate insulator includes forming oxide-nitride nanolaminate layers to trap charge in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers;

forming a number of bit lines coupled to the second source/drain region of each transistor along rows of the memory array;

forming a number of word lines coupled to the gate of each transistor along columns of the memory array;

forming a number of sourcelines formed in a bottom of the trenches between rows of the pillars and coupled to the first source/drain regions of each transistor along rows of pillars, wherein along columns of the pillars the first source/drain region of each transistor in column adjacent pillars couple to the sourceline in a shared trench such that a multistate cell transistor and a reference cell transistor share a common sourceline; and

wherein the number of vertical pillars can be programmed in a reverse direction to have a one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region by biasing a sourceline to a voltage higher than VDD, grounding a bitline, and selecting a gate by a wordline address.

112. The method of claim 111, wherein forming a number of sourcelines formed in a bottom of the trenches between rows of the pillars includes implanting a doped region in the bottom of the trench.

113. The method of claim 111, wherein, in forming a gate insulator above the channel region in the trenches along rows of pillars, the method includes forming a gate insulator having a thickness of at least 10 nanometers (nm).

114. The method of claim 111, wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of silicon nitride.

115. The method of claim 111, wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of aluminum nitride.

116. The method of claim 111, wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of gallium nitride.

117. The method of claim 111, wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of gallium aluminum nitride.

118. The method of claim 111, wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of tantalum aluminum nitride.

119. The method of claim 111, wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of titanium silicon nitride.

120. The method of claim 111, wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of titanium aluminum nitride.

121. The method of claim 111, wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of tungsten aluminum nitride.