Semiconductor device

• US 20040004255A1
• Filed: 06/13/2003
• Published: 01/08/2004
• Est. Priority Date: 07/04/2002
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Yoshimura, Tetsuo
• Granted Patent: US 6,867,475 B2
• Time in Patent Office: Days
• US Class Current: 257/379
• CPC Class Codes: H01L 27/0617 comprising components of the field-effect type H01L27/0251 takes precedence
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 Inductors

Abstract

There is provided a semiconductor device able to prevent performance degradation of an inductor element provided thereon. A high resistance region is provided below the inductor element formed on the semiconductor substrate. The high resistance region is formed deeper than the well regions of the p-channel and n-channel MOS transistors, thus preventing induction of an eddy current by the magnetic flux generated from the inductor element.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate having a predetermined substrate resistivity;

a device region formed in the semiconductor substrate;

impurity diffusion regions formed in the device region;

an inductor element formed on a first surface of the semiconductor substrate; and

a high resistance region formed in the semiconductor substrate facing the inductor element, said high resistance region having a resistivity higher than that of the semiconductor substrate.

2. A semiconductor device according to claim 1, wherein said high resistance region is formed in such a way that there is not any said impurity region existing between said high resistance region and a region of said semiconductor substrate having the substrate resistivity.

3. The semiconductor device according to claim 1, wherein said high resistance region is formed at a position farther than the impurity diffusion regions relative to the first surface of the semiconductor substrate.

4. The semiconductor device according to claim 1, wherein said high resistance region includes grooves.

5. The semiconductor device according to claim 1, wherein said high resistance region includes a porous portion.

6. The semiconductor device according to claim 1, wherein a depressed portion is formed on a second surface of the semiconductor substrate facing said inductor element.

7. The semiconductor device according to claim 6, wherein said depressed portion is formed to such a depth relative to the second surface that said high resistance region is able to be formed.

8. The semiconductor device according to claim 7 wherein said depressed portion includes a plurality of recesses.

9. The semiconductor device according to claim 1, wherein said high resistance region is formed of silicon oxide.

10. A method for producing a semiconductor device, comprising the steps of:

forming a high resistance region in a semiconductor substrate, said high resistance region having a resistivity higher than that of the semiconductor substrate;

forming a transistor in a device region formed around the high resistance region; and

forming an inductor element on the high resistance region,

wherein in the step of forming a transistor, the high resistance region is masked when implanting impurity elements to the device region.