Semiconductor latches and SRAM devices

• US 20040004298A1
• Filed: 04/14/2003
• Published: 01/08/2004
• Est. Priority Date: 07/08/2002
• Status: Active Grant

• Current Assignee: Liberty Patents LLC
• Original Assignee: Raminda U. Madurawe
• Inventors: Madurawe, Raminda U.
• Granted Patent: US 6,828,689 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

A new Static Random Access Memory (SRAM) cell using Thin Film Transistors (TFT) is disclosed. In a first embodiment, an SRAM cell comprises a strong inverter and a strong access device constructed on a semiconductor substrate layer, and a weak inverter and a weak access device constructed in a semiconductor thin film layer located vertically above the strong devices. The strong devices are used in the data read and write paths, and the weak devices are used for latch feed-back and sector data erase. This first embodiment is used for high density and high speed memory applications. In a second embodiment, an SRAM cell comprises thin film inverters and thin film access devices constructed in a semiconductor thin film layer located substantially above logic transistors. The TFT SRAM cell is buried above the logic gates of an Integrated Circuit to consume no extra Silicon real estate. This second embodiment is used for slow access and Look-Up-Tables type memory applications.

Claims

1. A semiconductor latch for integrated circuits adapted to have a first supply voltage and a second supply voltage substantially at a lower voltage level than said first supply voltage, the latch comprising:

a first and a second semiconductor layer, substantially different from each other;

a first inverter having a first conducting path coupled to said first supply voltage and an output, and a second conducting path coupled to said second supply voltage and said output, and said first and second conducting paths constructed in said first semiconductor layer; and

a second inverter having a first conducting path coupled to said first supply voltage and an output, and a second conducting path coupled to said second supply voltage and said output, and said first and second conducting paths constructed in said second semiconductor layer.

2. The device in claim 1 further comprising a first access device comprised of:

a conducting path constructed in said first semiconductor layer coupled to said output of first inverter and a first data line; and

a gate coupled to a first row line wherein, said gate at a first voltage level turning said conducting path on to substantially couple said first data line to said output of first inverter; and

said gate at a second voltage level turning said conducting path off to substantially de-couple said first data line from said output of first inverter.

3. The device in claim 1 further comprising a 3D semiconductor latch wherein:

a first semiconductor layer is a semiconductor substrate layer used to construct the two conducting paths of said first inverter; and

a second semiconductor layer is a poly-crystalline silicon thin film layer used to construct the two conducting paths of said second inverter;

wherein said second inverter is located substantially above said first inverter.

6. The device in claim 1 and claim 2 further comprising a single geometry of said first semiconductor layer.

7. The device in claim 1 and claim 4, wherein each of said first and second inverters further comprising an input to selectively couple one of said supply voltages to said output;

wherein

the inverter output is coupled to said second supply voltage when its input is at first supply voltage level; and

the inverter output is coupled to said first supply voltage when its input is at second supply voltage level; and

the input of first inverter is coupled to the output of second inverter, and the input of second inverter is coupled to the output of first inverter.

8. The device in claim 1 and claim 4 further comprising a second access device comprised of:

a conducting path constructed in said second semiconductor layer coupled to said output of second inverter and a second data line; and

a gate coupled to a second row line wherein, said gate at a first voltage level turning said conducting path on to substantially couple said second data line to said output of second inverter; and

said gate at a second voltage level turning said conducting path off to substantially de-couple said second data line from said output of second inverter.

9. The device in claim 1 and claim 4 comprising a thin film inverter.

10. The device in claim 6 further comprising:

a first stability point with the first inverter input at said first supply voltage level; and

a second stability point with the first inverter input at said second supply voltage level.

13. The method of claim 1 comprising:

depositing a first semiconductor layer;

fabricating a first inverter having a first conducting path coupled to said first supply voltage and an output, and a second conducting path coupled to said second supply voltage and said output, and said first and second conducting paths constructed in said first semiconductor layer;

depositing an isolation layer;

depositing a second semiconductor layer, substantially different from said first semiconductor layer;

fabricating a second inverter having a first conducting path coupled to said first supply voltage and an output, and a second conducting path coupled to said second supply voltage and said output, and said first and second conducting paths constructed in said second semiconductor layer; and

optimizing device and material properties of said first and said second inverter.

14. The method of claim 13, wherein depositing a first semiconductor layer is further comprised of:

forming a substantially single crystal semiconductor layer from one of wafer substrate, SOI substrate and thinned down SOI substrate layers; and

forming a semiconductor geometry comprising a conducting path of said first inverter.

16. The method of claim 13 and claim 15, wherein depositing a second semiconductor layer is further comprised of:

depositing a thin film semiconductor layer substantially above a semiconductor substrate layer, and substantially above a gate material used for said logic transistor gate construction; and

forming a semiconductor geometry comprising a conducting path of a said inverter.

17. The method of claim 1 and claim 4 comprises fabricating a conducting path of a thin film MOSFET transistor comprising:

forming a source, a body and a drain region;

forming said body region in between said source and drain regions;

doping said body region with opposite dopant type to said source and drain regions;

depositing an insulator region above said body region;

.

forming a gate region above said insulator region;

adapting said gate region to receive a voltage to modulate the majority carriers in said body region;

creating a conducting surface inversion state and a non-conducting surface accumulation state in said body region by two voltage levels applied to said gate region; and

depleting said majority carriers substantially from said body region during said conducting state.

18. The method in claim 1 and claim 4 comprises fabricating a thin film Gated-FET transistor with a conducting path comprised of:

forming a source, a channel and a drain region;

forming said channel region in between said source and drain regions;

doping said channel region to a resistive level with same dopant type as said source and drain regions;

depositing an insulator region above said channel region;

forming a gate region above said insulator region;

adapting said gate region to receive a voltage to modulate the majority carriers in said channel region;

creating a conducting surface accumulation state and a non-conducting depletion state in said channel region by two voltage levels applied to said gate region; and

depleting said majority carriers substantially from said channel region during said non-conducting state.

4. A semiconductor latch for integrated circuits adapted to have a first supply voltage and a second supply voltage substantially at a lower voltage level than said first supply voltage, the latch comprising:

a second semiconductor layer, substantially different from a first semiconductor substrate layer;

a first inverter having a first conducting path coupled to said first supply voltage and an output, and a second conducting path coupled to said second supply voltage and said output, and said first and second conducting paths constructed in said second semiconductor layer; and

a second inverter having a first conducting path coupled to said first supply voltage and an output, and a second conducting path coupled to said second supply voltage and said output, and said first and second conducting paths constructed in said second semiconductor layer.

5. The device in claim 4 further comprising a first access device comprised of:

a conducting path constructed in said second semiconductor layer coupled to said output of first inverter and a first data line; and

a gate coupled to a first row line wherein, said gate at a first voltage level turning said conducting path on to substantially couple said first data line to said output of first inverter; and

said gate at a second voltage level turning said conducting path off to substantially de-couple said first data line from said output of first inverter.

11. The device in claim 4, claim 5 and claim 8 further comprising a single geometry of said second semiconductor layer.

12. The device in claim 4 further comprising a second poly-crystalline silicon thin film layer of a 3D integrated circuit, wherein the poly-crystalline- silicon thin film is located substantially above a first semiconductor substrate layer, said semiconductor substrate layer comprising:

a logic transistor comprised of a gate, a source and a drain node, and one of said gate and drain nodes coupled to said output of said first inverter.

15. The method of claim 4 comprising:

depositing an isolation layer above a first semiconductor substrate region;

depositing a second semiconductor layer, substantially different from said first semiconductor substrate layer;

fabricating a first inverter having a first conducting path coupled to said first supply voltage and an output, and a second conducting path coupled to said second supply voltage and said output, and said first and second conducting paths constructed in said semiconductor thin film layer;

fabricating a second inverter having a first conducting path coupled to said first supply voltage and an output, and a second conducting path coupled to said second supply voltage and said output, and said first and second conducting paths constructed in said semiconductor thin film layer; and

optimizing device and material properties of said first and said second inverter.

19. A Static Random Access Memory Cell comprised of:

a strong inverter having an input and an output;

a strong access transistor coupled between said output of strong inverter and a data line, having a gate coupled to a first row line to selectively access said output of strong inverter;

a weak inverter having an input and an output, and said input of strong inverter coupled to output of weak inverter, and said output of strong inverter coupled to input of weak inverter;

a weak access transistor coupled between said output of weak inverter and a reset line, having a gate coupled to a second row line to selectively access said output of weak inverter;

a semiconductor substrate layer comprising high electron and hole mobility used to construct the conducting paths of strong inverter and strong access device; and

a semiconductor thin film layer comprising low electron and hole mobility used to construct the conducting paths of weak inverter and weak access device;

wherein said weak inverter and weak access device are located vertically above the strong inverter and strong access device.

20. A Static Random Access Memory Cell comprised of:

a first inverter having an input and an output;

a first access transistor coupled between said output of first inverter and a data line, having a gate coupled to a first row line to selectively access said output of first inverter;

a second inverter having an input and an output, and said input of first inverter coupled to output of second inverter, and said output of first inverter coupled to input of second inverter;

a second access transistor coupled between said output of second inverter and a reset line, having a gate coupled to a second row line to selectively access said output of second inverter; and

a semiconductor thin film layer comprising low electron and hole mobility used to construct the conducting paths of said first and second inverters and first and second access transistors;

wherein said inverters and transistors are located vertically above a logic transistor constructed on a semiconductor substrate layer having high electron and hole mobility.