Semiconductor integrated circuit with termination circuit

• US 20040004494A1
• Filed: 01/13/2003
• Published: 01/08/2004
• Est. Priority Date: 07/05/2002
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Song, Ho-Young
• Granted Patent: US 6,836,143 B2
• Time in Patent Office: Days
• US Class Current: 326/30
• CPC Class Codes: H04L 25/0298 Arrangement for terminating transmission lines

Abstract

A semiconductor integrated circuit device which includes a termination circuit for terminating a bus line. An impedance control circuit controls impedance of the termination circuit in accordance with impedance of an external reference resistor, so as to have the same or substantially the same impedance as that of the external reference resistor. A detection circuit detects whether the external reference resistor is electrically connected to the semiconductor integrated circuit, and disables the impedance control circuit based on a detection result.

Claims

1. A semiconductor integrated circuit comprising:

a termination circuit for terminating a bus line;

an impedance control circuit for controlling an impedance of the termination circuit depending on an impedance of an external reference resistance, so as to have the same or substantially the same impedance as that of the external reference resistance; and

a detection circuit for detecting whether the external reference resistance is electrically connected to the semiconductor integrated circuit and disabling the impedance control circuit depending on a detection result.

2. The semiconductor integrated circuit according to claim 1, wherein the termination circuit is disabled when the impedance control circuit is disabled.

3. The semiconductor integrated circuit according to claim 1, wherein the detection circuit is electrically connected to the external reference resistance, and activates a control signal for disabling the impedance control circuit when the external reference resistance is not connected to the semiconductor integrated circuit.

4. The semiconductor integrated circuit according to claim 1, wherein the impedance control circuit generates an impedance control code, which indicates an impedance value of the external reference resistance, depending on the impedance of the external reference resistance.

5. The semiconductor integrated circuit according to claim 4, wherein the detection circuit activates a control signal for disabling the impedance control circuit when the impedance control code indicates that the external reference resistance is not connected to the semiconductor integrated circuit.

10. The semiconductor integrated circuit according to claim 1, wherein the external reference resistance is an external reference resistor.

6. A semiconductor integrated circuit comprising:

a first pad connected to a bus line;

a second pad connected to an external reference resistance;

a first variable impedance circuit connected between a power supply voltage and the first pad;

a second variable impedance circuit connected between a ground supply voltage and the first pad;

a first comparator for comparing a voltage of the second pad with a reference voltage to output a count signal;

a counter for generating an impedance control signal for controlling impedance of the first and second variable impedance circuits, in response to the count signal; and

a detection circuit connected to the second pad, for detecting whether the external reference resistance is electrically connected to the semiconductor integrated circuit, wherein the detection circuit disables the first comparator and the counter when the external reference resistance is not connected to the semiconductor integrated circuit.

7. The semiconductor integrated circuit according to claim 6, wherein the detection circuit comprises:

a reference current source;

a current mirror connected to the reference current source and the second pad; and

a second comparator for comparing a voltage of the second pad with the reference voltage, the second comparator generating a control signal for disabling the first comparator and the counter when the voltage of the second pad is higher than the second reference voltage.

8. The semiconductor integrated circuit according to claim 7, wherein the first and second variable impedance circuits are disabled when the counter is disabled.

11. The semiconductor integrated circuit according to claim 6, wherein the external reference resistance is an external reference resistor.

9. A semiconductor integrated circuit comprising:

a first pad connected to a bus line;

a second pad connected to an external reference resistor;

a first variable impedance circuit connected between a power supply voltage and the first pad;

a second variable impedance circuit connected between a ground supply voltage and the first pad;

a comparator for comparing a voltage of the second pad with a reference voltage to output a count signal;

a counter for generating an impedance control code for controlling impedance of the first and second variable impedance circuits, in response to the count signal; and

a detection circuit for detecting whether the external reference resistor is electrically connected to the semiconductor integrated circuit, depending on the impedance control code,

wherein the detection circuit disables the first comparator and the counter when the impedance control code indicates that the external reference resistor is not connected to the semiconductor integrated circuit.

12. The semiconductor integrated circuit according to claim 9, wherein the external reference resistance is an external reference resistor.

13. A detection circuit, comprising:

a connection to a bonding pad of a semiconductor integrated circuit; and

a circuit for detecting whether a reference resistance, external to the semiconductor integrated circuit, is electrically connected to the semiconductor integrated circuit and disabling an impedance control circuit of the semiconductor integrated circuit depending on a detection result.

14. The detection circuit according to claim 13, wherein the circuit disables the an impedance control circuit of the semiconductor integrated circuit when the external reference resistance is not connected to the bonding pad.

15. The detection circuit according to claim 13, wherein the circuit disables the an impedance control circuit of the semiconductor integrated circuit when a voltage of the bonding pad is higher than a reference voltage applied to the circuit.

16. The detection circuit according to claim 13, wherein the circuit disables the impedance control circuit of the semiconductor integrated circuit by outputting a disable signal.

17. The detection circuit according to claim 13, wherein the circuit disables the impedance control circuit of the semiconductor integrated circuit.

18. The detection circuit according to claim 13, said circuit including,

a reference current source,

a current mirror connected to the reference current source and the bonding pad, and

a comparator for comparing a voltage of the bonding pad with a reference voltage, the comparator generating a control signal for disabling impedance control circuit when the voltage of the bonding pad is higher than the reference voltage.

19. The detection circuit according to claim 13, said circuit including an OR gate for receiving an impedance control signal from the impedance control circuit and outputting a disable signal.

20. The detection circuit according to claim 13, wherein the external reference resistance is an external reference resistor.

21. The semiconductor integrated circuit including the detection circuit of claim 13.