System and method for multi-modal memory controller system operation

• US 20040006674A1
• Filed: 07/05/2002
• Published: 01/08/2004
• Est. Priority Date: 07/05/2002
• Status: Active Grant

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Tayler, Michael Kennard, Hargis, Jeff G., Letey, George Thomas
• Granted Patent: US 6,854,043 B2
• Time in Patent Office: Days
• US Class Current: 711/156
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types

Abstract

A memory controller system for processing memory access requests comprising a first memory controller operable to address a first plurality of memory modules a second memory controller operable to address a second plurality of memory modules, the first and second memory controllers configurable to process a memory transaction in an operational mode of the memory controller system selected from the group consisting of an independent cell mode, a multiplexer-mode (mux-mode), and a lockstep mode, and a bus interface block operable to convey the memory transaction to both of the first and second memory controllers is provided.

Claims

1. A memory controller system for processing memory access requests, comprising:

a first memory controller operable to address a first plurality of memory modules;

a second memory controller operable to address a second plurality of memory modules, the first and second memory controllers configurable to process a memory transaction in an operational mode of the memory controller system selected from the group consisting of an independent cell mode, a multiplexer-mode (mux-mode), and a lockstep mode; and

a bus interface block operable to convey the memory transaction to both of the first and second memory controllers.

2. The memory controller system according to claim 1, wherein the operational mode is one of the independent cell mode and the mux-mode, the memory transaction accepted and processed by one of the first and second memory controllers.

3. The memory controller system according to claim 1, wherein the operational mode is the lockstep mode, the memory transaction accepted and processed by each of the first and second memory controllers.

4. The memory controller system according to claim 1, wherein the first and second memory controllers further comprise a respective memory bank address table each operable to map physical address to, and maintain page state data of, a memory space provided by the respective first and second plurality of memory modules.

5. The memory controller system according to claim 1, wherein a quarter-cache line data transfer is performed with a one-clock cycle reduction in latency when the memory controller system is configured to operate in the lockstep mode than operably possible when configured to operate in the independent cell mode.

6. The memory controller system according to claim 1, wherein each of the first and second memory controllers further comprises a respective heap operable to maintain a plurality of memory transactions therein.

7. The memory controller system according to claim 1, wherein each of the first and second memory controllers further comprises a respective scheduler operable to receive a memory command, and each scheduler operable to output the memory command to its respective plurality of memory modules.

8. The memory controller system according to claim 4, wherein the memory controller system is configured to operate in one of the independent cell mode and the mux-mode, wherein the memory transaction is accepted by one of the memory bank address tables.

9. The memory controller system according to claim 4, wherein the memory controller system is configured to operate in the lockstep mode, the memory transaction is accepted by both memory bank address tables.

10. The memory controller system according to claim 7, wherein the memory controller system is configured to operate in the lockstep mode, each scheduler outputs the memory command in synchronization to their respective plurality of memory modules.

11. The memory controller system according to claim 1, wherein each of the first and second memory controllers further comprises a respective configuration register set that is firmware writeable, the operational mode of the memory controller system being selected dependent on a respective logic state of the configuration register sets.

12. The memory controller system according to claim 11, wherein each of the configuration registers sets have an identical logic state, the memory controller system operable in the lockstep mode.

13. The memory controller system according to claim 1, further comprising:

a read data storage operable to store a plurality of data transfers from each of the first and second plurality of memory modules; and

a memory control data block comprising a critical word multiplexer operable to receive read data from the first and second plurality of memory modules and convey the read data to the read data storage.

14. The memory controller system according to claim 13, wherein the critical word multiplexer conveys the read data to the read data storage in one of a plurality of formats selectable by a critical word multiplexer control signal applied to a select input thereof.

15. The memory controller system according to claim 14, wherein the critical word multiplexer includes a bit indicative of the mux-mode operational state, a bit indicative of the lockstep mode, and a bit field indicative of a critical word order.

16. The memory controller system according to claim 13, wherein the critical word multiplexer is operable to perform alignment and merge operations on the read data prior to conveyance of the data to the read data storage.

17. The memory controller system according to claim 13, wherein the critical word multiplexer is operable to merge read data from the first plurality of memory modules with read data from the second plurality of memory modules when the memory controller system is configured to operate in the lockstep mode.

18. The memory controller system according to claim 17, wherein the merged data comprises the smallest read data transfer size that may be made between the read data storage and the bus interface block, conveyance of the merged data occurring on a single clock cycle.

19. A method of processing a memory access request in a memory controller system, comprising:

receiving, by the memory control system, a memory transaction;

conveying the memory transaction to each of a first memory controller and a second memory controller;

issuing, by the first memory controller, a memory command to a plurality of memory modules coupled with the first memory controller; and

issuing, by the second memory controller, a memory command to a plurality of memory modules coupled with the second memory controller, wherein the issuing of the memory commands by the first and second memory controllers are performed in synchronization.

20. The method according to claim 19, further comprising:

respectively issuing, by the first and second memory controllers, a memory command to each of the plurality of memory modules; and

merging a plurality of data bits received from the plurality of memory modules of the first memory controller with a plurality of data bits received from the second plurality of memory modules.

21. The method according to claim 20, further comprising conveying the merged data bits to a cache memory of a processor, the merged data bits comprising a smallest data transfer size operable to be conveyed to the cache memory, conveyance of the merged data occurring on a single clock cycle.

22. The method according to claim 19, further comprising inputting the plurality of data bits of the first and second memory controllers into a respective source input of an alignment and merge circuit.

23. The method according to claim 22, further comprising sourcing, by the alignment and merge circuit, a first output comprised of the merged data bits in a first critical word order and a second output comprised of the merged data bits in a second critical word order.

24. The method according to claim 23, wherein the first and second outputs are applied to a source input of a multiplexer circuit.

25. The method according to claim 24, wherein a control signal is applied to an input of the multiplexer for selecting one of the first outputs and the second outputs for conveyance to a memory cache.

26. A method of configuring a memory controller system, comprising:

indicating selection of a lockstep mode of the controller system; and

transferring, to a first and second memory controller, configuration data writes addressed to a configuration register set of the first memory controller.

27. The method according to claim 26, further comprising discarding configuration data writes addressed to a configuration register set of the second memory controller.

28. The method according to claim 26, wherein indicating selection of a lockstep mode further comprises setting a programmable register with a bit value interpreted by a system configuration bus protocol controller as indicating selection of a lockstep mode.