Processor and instruction control method

• US 20040006686A1
• Filed: 01/21/2003
• Published: 01/08/2004
• Est. Priority Date: 07/05/2002
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Yoshida, Toshio
• Granted Patent: US 7,590,827 B2
• Time in Patent Office: Days
• US Class Current: 712/218
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3842 Speculative instruction execution

Abstract

A latest register update buffer which stores latest register update data is allocated and prepared every general register for storing source data. A latest register update processing unit stores a value in the general register as latest register update data into the latest register update buffer when a register update instruction is not speculatively executed, and overwrites a result of the speculative execution when the instruction is speculatively executed. Upon instruction decoding, a matching processing unit reads out the latest register update data from the latest register update allocation buffer and stores it into a data area in a reservation station.

Claims

1. A processor comprising:

a buffer which is allocated every general register for storing source data and stores latest register update data;

a buffer control unit which stores said latest register update data into said buffer in accordance with the presence or absence of speculative execution of a register update instruction; and

a storage control unit which reads out the latest register update data from said buffer and stores it into a data area in a reservation station upon instruction decoding.

2. A processor according to claim 1, wherein said buffer control unit stores the latest register update data obtained by the speculative execution of the instruction into said buffer.

3. A processor according to claim 1, wherein said buffer control unit comprises:

an address latch which holds an allocation address of said buffer;

an update pending latch which holds a pending bit showing that said register update data is update-pending; and

a logic control unit which stores the latest register update data into said buffer in an updating cycle by the speculative execution of the instruction under conditions such that an update address of the register update data coincides with the allocation address in said address latch, the pending bit is held in said update pending latch, and an updating cycle valid signal is obtained.

4. A processor according to claim 1, wherein said buffer control unit stores the data in the general register into said buffer when the instruction which is being speculatively executed is abandoned.

5. A processor according to claim 4, wherein said buffer control unit reads out the data from said general register and stores it into said buffer in one blank cycle after the instruction which is being speculatively executed is abandoned.

6. A processor according to claim 1, wherein said buffer control unit reads out the latest register update data with reference to said buffer by a register address and stores it into the data area in said reservation station upon instruction decoding.

7. An instruction control method of a processor which executes instructions by dynamic pipeline scheduling, comprising:

a buffer control step wherein latest register update data is stored into a buffer which is allocated every general register for storing source data in accordance with the presence or absence of speculative execution of a register update instruction; and

a storage control step wherein said latest register update data is read out from said buffer and stored into a data area in a reservation station upon instruction decoding.

8. A method according to claim 7, wherein in said buffer control step, the latest register update data obtained by the speculative execution of the instruction is stored into said buffer.

9. A method according to claim 7, wherein said buffer control step comprises the steps of:

holding an allocation address of said buffer into an address latch;

holding a pending bit showing that said register update data is update-pending into an update pending latch; and

storing the latest register update data into said buffer in an updating cycle by the speculative execution of the instruction under conditions such that an update address of the register update data coincides with the allocation address in said address latch, the pending bit is held in said update pending latch, and an updating cycle valid signal is obtained.

10. A method according to claim 7, wherein in said buffer control step, the data in the general register is stored into said buffer when the instruction which is being speculatively executed is abandoned.

11. A method according to claim 10, wherein in said buffer control step, the data is read out from said general register and stored into said buffer in one blank cycle after the instruction which is being speculatively executed is abandoned.

12. A method according to claim 7, wherein in said buffer control step, the latest register update data is read out with reference to said buffer by a register address and stored into the data area in said reservation station upon instruction decoding.

13. A processor comprising:

a buffer which is allocated every register for storing a condition code and stores latest condition code register update data;

a buffer control unit which sets the latest condition code register update data into said buffer in accordance with the presence or absence of speculative execution of a condition code register update instruction; and

a storage control unit which reads out the latest condition code register update data from said buffer and stores it into a condition code data area in a reservation station upon instruction decoding.

14. A processor according to claim 13, wherein said buffer control unit stores the latest condition code register update data obtained by the speculative execution of the instruction into said buffer.

15. A processor according to claim 14, wherein said buffer control unit comprises:

an address latch which holds an allocation address of said buffer;

an update pending latch which holds a pending bit showing that said condition code register update data is update-pending; and

a logic control unit which stores the latest condition code register update data into said buffer in an updating cycle by the speculative execution of the instruction under conditions such that an update address of the condition code register update data coincides with the allocation address in said address latch, the pending bit is held in said update pending latch, and an updating cycle valid signal is obtained.

16. A processor according to claim 13, wherein said buffer control unit sets the data in said condition code register into said buffer when the instruction which is being speculatively executed is abandoned.

17. A processor according to claim 16, wherein said buffer control unit reads out the data from said condition code register and stores it into said buffer in one blank cycle after the instruction which is being speculatively executed is abandoned.

18. A processor according to claim 13, wherein said buffer control unit reads out the latest condition code register update data with reference to said buffer by the address in the condition code register and stores it into the condition code data area in said reservation station upon instruction decoding.

19. An instruction control method of a processor which executes instructions by dynamic pipeline scheduling, comprising:

a buffer control step wherein latest condition code register update data is set into a buffer which is allocated every register for storing a condition code in accordance with the presence or absence of speculative execution of a condition code register update instruction; and

a storage control step wherein the latest condition code register update data is read out from said buffer and stored into a condition code data area in a reservation station upon instruction decoding.

20. A method according to claim 19, wherein in said buffer control step, the latest condition code register update data obtained by the speculative execution of the instruction is stored into said buffer.

21. A method according to claim 20, wherein said buffer control step comprises the steps of:

holding an allocation address of said buffer into an address latch;

holding a pending bit showing that said condition code register update data is update-pending into an update pending latch; and

storing the latest condition code register update data into said buffer in an updating cycle by the speculative execution of the instruction under conditions such that an update address of the condition code register update data coincides with the allocation address in said address latch, the pending bit is held in said update pending latch, and an updating cycle valid signal is obtained.

22. A method according to claim 19, wherein in said buffer control step, the data in said condition code register is stored into said buffer when the instruction which is being speculatively executed is abandoned.

23. A method according to claim 22, wherein in said buffer control step, the data is read out from said condition code register and stored into said buffer in one blank cycle after the instruction which is being speculatively executed is abandoned.

24. A method according to claim 19, wherein in said buffer control step, the latest condition code register update data is read out with reference to said buffer by the address in the condition code register and stored into the condition code data area in said reservation station upon instruction decoding.