Processor and instruction control method

• US 20040006687A1
• Filed: 01/21/2003
• Published: 01/08/2004
• Est. Priority Date: 07/05/2002
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Yoshida, Toshio
• Granted Patent: US 7,269,716 B2
• Time in Patent Office: Days
• US Class Current: 712/220
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/3828 with global bypass, e.g. between pipelines, between clusters
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/384 Register renaming

Abstract

A following CC read instruction which is decoded simultaneously with a previous CC update instruction is developed into a multiflow. The first flow is set to a no-operation. A CC renaming update is executed by a CC renaming map update processing unit by the decoding of the previous CC update instruction. The resultant instruction is stored into a CC read instruction multiflow instruction word register. At the next second flow, the CC read instruction is issued from the multiflow instruction word register and, in a state where another instruction is not simultaneously issued, a CC renaming map is referred to by a CC renaming map reference processing unit by the decoding of the CC read instruction.

Claims

1. A processor comprising:

an instruction issuing unit which issues fetched and decoded instructions to a reservation station by an in-order;

an instruction executing unit which executes the instructions held in said reservation station by out-of-order;

a committing unit which discriminates a commitment of the instructions executed by said instruction executing unit and completes them by the in-order;

an instruction fetching unit which simultaneously fetches a plurality of instructions including a condition code update instruction serving as a previous instruction and a condition code read instruction serving as a following instruction into said instruction issuing unit;

a renaming map update processing unit which, at a decoding stage of said previous instruction, when a renaming register which holds update data until the commitment of the instruction is allocated, condition code information including a register number of said renaming register is registered into a renaming map for the condition code;

a renaming map reference processing unit which develops said following instruction into a multiflow, transfers and holds the multiflow instruction into a multiflow instruction word register by setting the same decoding stage as that of said previous instruction to a no-operation, and at the next decoding stage of the following instruction, stores the condition code information of the previous instruction registered in said renaming map for the condition code into a source register area of a previous instruction allocation entry stored in said reservation station;

a forward control discriminating unit which, at a priority stage of said previous instruction, compares the renaming register number of the execution result with the renaming register number in the previous instruction allocation entry in said reservation station and, when they coincide, notifies said instruction executing unit of completion of preparation for forward control of condition data for the following instruction and allows said instruction executing unit to execute the instruction; and

a condition data write processing unit which, at an updating stage of said previous instruction, stores condition code data obtained as an execution result of the previous instruction into the source register area of the previous instruction allocation entry stored in said reservation station.

2. A processor according to claim 1, wherein said renaming map update processing unit stores an update pending bit into said renaming map for the condition code together with the register number of the renaming register allocated to said condition code update instruction.

3. A processor according to claim 2, wherein said renaming map reference processing unit stores the update pending bit of the previous instruction registered in said renaming map for the condition code and a register number of the renaming register for the condition code into the area for the update pending bit of the source register in the previous instruction allocation entry of said reservation station and the renaming register number.

4. A processor according to claim 3, wherein said forward control discriminating unit compares a renaming address number of the execution result of the previous instruction with the renaming register number in the previous instruction allocation entry in said reservation station under a condition that said update pending bit has been set to 1, when they coincide, sets a bypass ready bit for the condition code into a bypass ready area of the source register in the previous instruction allocation entry in said reservation station, and notifies the instruction executing unit of the completion of the preparation for the forward control of the condition data for the following instruction on the basis of the bypass ready bit for the condition code.

5. A processor according to claim 4, wherein said condition data write processing unit stores the condition data obtained as an arithmetic operation result of the previous instruction into the source register area subsequent to the condition code update pending bit, the address number of the renaming register for the condition code, and the bypass ready bit for the condition code in the previous instruction allocation entry stored in said reservation station.

6. An instruction control method of a processor, comprising:

an instruction issuing step wherein instructions which were fetched and decoded are issued to a reservation station by in-order;

an instruction executing step wherein the instructions held in said reservation station are executed by out-of-order;

a committing step wherein a commitment of the instructions executed in said instruction executing step is discriminated and the instructions are completed by the in-order;

an instruction fetching step wherein a plurality of instructions including a condition code update instruction serving as a previous instruction and a condition code read instruction serving as a following instruction are simultaneously fetched into an instruction issuing unit;

a renaming map updating step wherein at a decoding stage of said previous instruction, when a renaming register which holds update data until the commitment of the instruction is allocated, condition code information including a register number of the renaming register is registered into a renaming map for the condition code;

a renaming map referring step wherein said following instruction is developed into a multiflow, the multiflow instruction is transferred and held into a multiflow instruction word register by setting the same decoding stage as that of said previous instruction to a no-operation, and at the next decoding stage of the following instruction, condition code information of the previous instruction registered in said renaming map for the condition code is stored into a source register area in a previous instruction allocation entry stored in said reservation station;

a forward control discriminating step wherein at a priority stage of said previous instruction, a renaming address number of an execution result is compared with a renaming register number in the previous instruction allocation entry in said reservation station, and when they coincide, an instruction executing unit is notified of completion of preparation of forward control of condition data for the following instruction and is allowed to execute the instruction; and

a condition data writing step wherein at an update stage of the previous instruction, condition code data obtained as an execution result of the previous instruction is stored into the source register area in the previous instruction allocation entry stored in said reservation station.

7. A method according to claim 6, wherein in said renaming map updating step, an update pending bit is stored into said renaming map for the condition code together with the register number of the renaming register allocated to said condition code update instruction.

8. A method according to claim 7, wherein in said renaming map referring step, an update pending bit of the previous instruction registered in said renaming map for the condition code and a register number of the renaming register for the condition code are stored into the area for the update pending bit of the source register in the previous instruction allocation entry of said reservation station and the renaming register number.

9. A method according to claim 8, wherein in said forward control discriminating step, the renaming address number of the execution result of the previous instruction is compared with the renaming register number in the previous instruction allocation entry in said reservation station under a condition that said update pending bit has been set to 1, when they coincide, a bypass ready bit for the condition code is set into a bypass ready area of the source register in the previous instruction allocation entry in said reservation station, and the instruction executing unit is notified of the completion of the preparation for the forward control of the condition data for the following instruction on the basis of the bypass ready bit for the condition code.

10. A method according to claim 9, wherein in said condition data writing step, the condition data obtained as an arithmetic operation result of the previous instruction is stored into the source register area subsequent to the condition code update pending bit, the address number of the renaming register for the condition code, and the bypass ready bit for the condition code in the previous instruction allocation entry stored in said reservation station.