Mirrored tag snoop optimization

• US 20040006716A1
• Filed: 07/02/2002
• Published: 01/08/2004
• Est. Priority Date: 07/02/2002
• Status: Active Grant

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Verdun, Gary, Schuckle, Richard W.
• Granted Patent: US 7,017,054 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/32 Means for saving power

Abstract

A method and system for reducing snoop traffic on a processor bus coupling a cache memory and a processor. The processor is unable to perform a snoop operation while operating in a lower power state to conserve power. A copy of cache tag is maintained in a memory controller coupled to the processor bus. The memory controller performs snoop operations on the copy of the cache tag while the processor is placed in the lower power state. The processor exits the lower power state when an access to a modified cached line occurs.

Claims

1. A method of reducing power consumed by a processor in an information handling system having the processor coupled to a memory controller, the method comprising the step of:

providing a processor having a lower power state and in a higher power state, wherein the processor does not perform a snoop operation while in the lower power state; and

performing the snoop operation with a memory controller, wherein the memory controller performs the snoop operation when the processor is in the lower power state.

2. The method of claim 1, wherein the step of performing the snoop operation further comprises the steps of:

redirecting the snoop operation from the processor to the memory controller; and

determining whether an address of a memory location accessed has a match in a copy of a cache tag stored in the memory controller.

3. The method of claim 1, wherein the lower power state is a C2 or C3 state.

4. The method of claim 1, wherein the higher power state is a C0 or C1 state.

5. The method of claim 1, wherein the snoop operation is generated when a device coupled to the information handling system performs a read or a write operation to a main memory location of the information handling system.

6. A method of reducing snoop traffic on a processor bus coupling a cache memory and a processor, the method comprising the steps of:

maintaining a copy of a cache tag in a memory controller, wherein the memory controller is coupled to a processor bus;

performing a snoop operation with the memory controller on the copy of the cache tag while the processor is in a lower power state, wherein the processor does not perform the snoop operation while operating in the lower power state; and

changing the processor from the lower power state to the higher power state when an access to a modified cached line occurs.

7. The method of claim 6, wherein the cache tag is a directory of memory locations in the cache memory.

8. The method of claim 6, wherein the step of maintaining the copy of the cache tag in the memory controller comprises the step of writing cache tag information to a mirror tag included in the memory controller when the cache tag information is written to the cache memory.

9. The method of claim 6, wherein the step of maintaining the copy of the cache tag in the memory controller comprises the step of writing cache tag information to a mirror tag included in the memory controller before the processor enters the lower power state.

10. The method of claim 6, wherein the step of performing the snoop operation further comprises the steps of:

redirecting the snoop operation from the processor to the memory controller; and

determining whether an address of a memory location accessed has a match in the copy of the cache tag stored in the memory controller.

11. The method of claim 6, wherein the step of reducing snoop traffic further comprises the step of maintaining the processor in the lower power state when an access to an unmodified cached line occurs.

12. The method of claim 6, wherein the snoop operation is generated when a device coupled to the information handling system performs a read or a write operation to a main memory location of the information handling system.

13. An information handling system, comprising:

a processor, wherein the processor performs a snoop operation when in a higher power state and does not perform the snoop operation when in a lower power state;

a memory coupled to the processor;

a cache memory coupled to the processor and the memory;

a processor bus, wherein the processor bus is coupled to the processor and a memory controller; and

the memory controller being enabled to perform the snoop operation while the processor is in the lower power state.

14. The system of claim 13, wherein the memory controller performs the snoop operation by maintaining a copy of a cache tag, wherein the cache tag is a directory of memory locations in the cache memory.

15. The system of claim 14, wherein the copy of the cache tag is maintained in the memory controller by writing cache tag information to a mirror tag included in the memory controller when the cache tag information is written to the cache memory.

16. The system of claim 14, wherein the copy of the cache tag is maintained in the memory controller by the processor writing cache tag information to a mirror tag included in the memory controller before entering the lower power state.

17. The system of claim 13, wherein the processor redirects the snoop operation to the memory controller by determining whether an address of the memory accessed has a match in a copy of the cache tag stored in the memory controller.

18. The system of claim 13, wherein the processor is maintained in the lower power state when an access to an unmodified cached line occurs.

19. The system of claim 13, wherein the snoop operation occurs when a device coupled to the information handling system performs a read or a write operation to the memory.

20. A information handling system comprising:

a processor;

a memory coupled to the processor;

a cache memory coupled to a processor bus, wherein the processor bus is coupled to the processor and a memory controller; and

wherein the memory controller is adapted to;

store a copy of a cache tag in the memory controller;

perform a snoop operation with the memory controller on the copy of the cache tag when the processor is in a lower power state and thereby does not perform the snoop operation; and

changing the processor from the lower power state to the higher power state when an access to a modified cached line occurs.

21. The system of claim 20, wherein the cache tag is a directory of memory locations in the cache memory.

22. The system of claim 20, wherein the copy of the cache tag is stored in the memory controller by writing cache tag information to the memory controller when the cache tag information is written to the cache memory.

23. The system of claim 20, wherein the copy of cache tag is stored in the memory controller by the processor writing cache tag information to the memory controller before entering the lower power state.

24. The system of claim 20, wherein performing the snoop operation further comprises:

redirecting the snoop operation from the processor to the memory controller; and

determining whether an address of a memory location accessed has a match in the copy of the cache tag stored in the memory controller.

25. The system of claim 20, wherein the processor is maintained in the lower power state when an access to an unmodified cached line occurs.

26. The system of claim 20, wherein the snoop operation occurs when a device coupled to the information handling system performs a read or a write operation to the memory.

27. A computer-readable medium having a computer program accessible therefrom, wherein the computer program comprises instructions for:

maintaining a processor of a information handling system in a lower power state, wherein the processor does not perform a snoop operation while in the lower power state; and

redirecting the snoop operation from the processor to a memory controller of the information handling system, wherein the redirected snoop operation enables a reduction in power consumed by the processor maintained in the lower power state.

28. A computer-readable medium having a computer program accessible therefrom, wherein the computer program comprises instructions for:

storing a copy of a cache tag in a memory controller of a information handling system, wherein the memory controller is coupled to a processor included in the information handling system;

performing a snoop operation with the memory controller on the copy of the cache tag while the processor is placed in a lower power state, wherein the processor does not perform the snoop operation while in the lower power state; and

changing the processor from the lower power state to the higher power state when an access to a modified cached line occurs.