Method and apparatus for improving network router line rate performance by an improved system for error checking

• US 20040006725A1
• Filed: 07/03/2002
• Published: 01/08/2004
• Est. Priority Date: 07/03/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Lakshmanamurthy, Sridhar, Narad, Charles E., Liu, Kin-Yip, Huston, Lawrence B., Pun, Yim
• Granted Patent: US 7,103,821 B2
• Time in Patent Office: Days
• US Class Current: 714/42
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's

Abstract

A method and apparatus for improving network router line rate performance by an improved system for error correction is described. In an embodiment of the present invention, error correction is performed by a hardware-based system within the processing engine of a router'"'"'s network processor.

Claims

1. A system for network data transfer comprising:

an intermediate device to pass a data set from a first device to at least one of a plurality of locations in a memory device, said intermediate device having an execution unit and an error correction device, wherein

said execution unit is to determine where in said memory device to pass said data set; and

said error correction device is a hardware device to operate in parallel with said execution unit.

2. The system of claim 1, wherein said memory device is Dynamic Random Access Memory (DRAM).

3. The system of claim 1, wherein said intermediate device is a processing engine.

4. The system of claim 1, wherein said first device is a media interface to translate said data set from a first protocol to a second protocol.

5. The system of claim 4, wherein said first protocol is Internet Protocol (IP) and includes an error check term for said data set.

6. The system of claim 5, wherein said second protocol is an encapsulation of said Internet Protocol (IP) with said error check term and said error correction device utilizes an error-detecting polynomial.

7. The system of claim 6, wherein said second protocol is ATM (Asynchronous Transfer Mode) Adaptation Layer 5 (AAL5).

8. The system of claim 6, wherein said error correction device utilizes an error-detecting polynomial.

9. The system of claim 8, wherein said error correction device processes said data set to yield a value, said value to be compared to said error check term for error detection.

10. The system of claim 9, wherein said error-detecting polynomial is hardware-driven 32-bit Cyclic Redundancy Code (CRC-32).

11. The system of claim 9, wherein said error correction device includes a linear shift register.

12. A method for network data transfer comprising:

transferring a data set, by an intermediate device, from a first device to at least one of a plurality of locations in a memory device, said intermediate device having an execution unit and an error correction device;

determining, by said execution unit, where in said memory device to transfer said data set; and

processing said data set, by said error correction device, in parallel with said execution unit.

13. The method of claim 12, wherein said memory device is Dynamic Random Access Memory (DRAM).

14. The method of claim 12, wherein said intermediate device is a processing engine.

15. The method of claim 12, wherein said first device is a media interface to translate said data set from a first protocol to a second protocol.

16. The method of claim 15, wherein said first protocol is Internet Protocol (IP) and includes an error check term for said data set.

17. The method of claim 16, wherein said second protocol is an encapsulation of said Internet Protocol (IP) with said error check term and said error correction device utilizes an error-detecting polynomial.

18. The method of claim 17, wherein said second protocol is ATM (Asynchronous Transfer Mode) Adaptation Layer 5 (AAL5).

19. The method of claim 17, wherein said error correction device utilizes an error-detecting polynomial.

20. The method of claim 19, wherein said error correction device processes said data set to yield a value, said value to be compared to said error check term for error detection.

21. The method of claim 20, wherein said error-detecting polynomial is hardware-driven 32 bit Cyclic Redundancy Code (CRC-32).

22. The method of claim 20, wherein said error correction device includes a linear shift register.

23. An apparatus for network data transfer comprising:

a processing engine to forward a data set, having an error check term, from a media interface to at least one location in a memory device, said media interface to translate said data set from a first protocol to a second protocol and said processing engine including an execution unit to determine where in said memory device to forward said data set; and

an error-correction device including a linear shift register to compare said error check term to a value computed by said linear shift register.

24. The system of claim 23, wherein said memory device is Dynamic Random Access Memory (DRAM).

25. The system of claim 24, wherein said media interface is an Asynchronous Transfer Mode (ATM) Framer.

26. The system of claim 25, wherein said first protocol is Internet Protocol (IP) and said second protocol is ATM (Asynchronous Transfer Mode) Adaptation Layer 5 (AAL5).

27. The system of claim 26, wherein said error-correction device utilizes 32-bit Cyclic Redundancy Code (CRC-32).

28. A system for network data transfer comprising:

a line card including a processing engine, said processing engine to forward a data set having an error check term from a media interface to at least one location in a memory device; and

an error-correction device including a linear shift register to compare said error check term to a value computed by said linear shift register, wherein

said media interface is to translate said data set from a first protocol to a second protocol and is coupled to a network; and

said processing engine includes an execution unit to determine where in said memory device to forward said data set.

29. The system of claim 28, wherein said memory device is Dynamic Random Access Memory (DRAM) and said media interface is an Asynchronous Transfer Mode (ATM) Framer.

30. The system of claim 29, wherein said first protocol is Internet Protocol (IP) and said second protocol is ATM (Asynchronous Transfer Mode) Adaptation Layer 5 (AAL5).