Folded bit line DRAM with vertical ultra thin body transistors

• US 20040007721A1
• Filed: 05/05/2003
• Published: 01/15/2004
• Est. Priority Date: 02/09/2001
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Granted Patent: US 6,995,057 B2
• Time in Patent Office: Days
• US Class Current: 257/204
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/482 Bit lines

Abstract

A folded bit line DRAM device is provided. The folded bit line DRAM device includes an array of memory cells. Each memory cell in the array of memory cells includes a pillar extending outwardly from a semiconductor substrate. Each pillar includes a single crystalline first contact layer and a single crystalline second contact layer separated by an oxide layer. A single crystalline vertical transistor is formed along alternating sides of the pillar within a row of pillars. The single crystalline vertical transistor includes an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer, an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer, and an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions. A plurality of buried bit lines are formed of single crystalline semiconductor material and disposed below the pillars in the array memory cells for interconnecting with the first contact layer of column adjacent pillars in the array of memory cells. Further, a plurality of word lines are included. Each word line is disposed orthogonally to the plurality of buried bit lines in a trench between rows of the pillars for addressing alternating body regions of the single crystalline vertical transistors that are adjacent to the trench.

Claims

1. A folded bit line DRAM device, comprising:

an array of memory cells formed in rows and columns, wherein each memory cell in the array of memory cells includes;

a pillar extending outwardly from a semiconductor substrate, wherein the pillar includes a single crystalline first contact layer and a single crystalline second contact layer separated by an oxide layer;

a single crystalline vertical transistor formed along alternating sides of the pillar within a row of pillars, wherein the single crystalline vertical transistor includes;

an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;

an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer; and

an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions;

a plurality of buried bit lines formed of single crystalline semiconductor material and disposed below the pillars in the array memory cells for interconnecting with the first contact layer of column adjacent pillars in the array of memory cells; and

a plurality of word lines, each word line disposed orthogonally to the plurality of buried bit lines in a trench between rows of the pillars for addressing alternating body regions of the single crystalline vertical transistors that are adjacent to the trench.

2. The folded bit line DRAM device of claim 1, wherein the ultra thin single crystalline vertical body region includes a channel having a vertical length of less than 100 nanometers.

3. The folded bit line DRAM device of claim 1, wherein the ultra thin single crystalline vertical body region has a horizontal width of less than 10 nanometers.

4. The folded bit line DRAM device of claim 1, wherein the ultra thin single crystalline vertical body region is formed from solid phase epitaxial growth.

5. A folded bit line DRAM device, comprising:

an array of memory cells, wherein each memory cell in the array of memory cells includes;

a pillar extending outwardly from a semiconductor substrate, wherein the pillar includes a single crystalline first contact layer and a single crystalline second contact layer separated by an oxide layer;

a single crystalline vertical transistor formed along side of the pillar, wherein the single crystalline vertical transistor includes;

an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;

an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer;

an ultra thin single crystalline vertical body region formed along alternating sides of the pillar within a row of pillars and coupling the first and the second source/drain regions; and

a gate opposing the vertical body region and separated therefrom by a gate oxide;

a plurality of buried bit lines formed of single crystalline semiconductor material and disposed below the pillars in the array memory cells for interconnecting with the first contact layer of column adjacent pillars in the array of memory cells; and

a plurality of word lines, each word line disposed orthogonally to the plurality of buried bit lines in a trench between rows of the pillars for addressing gates of the single crystalline vertical transistors that are adjacent to the trench in alternating pillars along a row of pillars.

6. The folded bit line DRAM device of claim 5, wherein the plurality of buried bit lines are more heavily doped than the first contact layer and are formed integrally with the first contact layer.

7. The folded bit line DRAM device of claim 5, wherein the ultra thin single crystalline vertical body region includes a p-type channel having a vertical length of less than 100 nanometers.

8. The folded bit line DRAM device of claim 7, wherein the ultra thin single crystalline vertical body region has a horizontal width of less than 10 nanometers

9. The folded bit line DRAM device of claim 5, wherein the pillar extends outwardly from an insulating portion of the semiconductor substrate.

10. The folded bit line DRAM device of claim 5, wherein the semiconductor substrate includes a silicon on insulator substrate.

11. The folded bit line DRAM device of claim 5, wherein the gate includes a horizontally oriented gate, wherein a vertical side of the horizontally oriented gate has a length of less than 100 nanometers.

12. The folded bit line DRAM device of claim 5, wherein the gate includes a vertically oriented gate having a vertical length of less than 100 nanometers.

13. A folded bit line DRAM device, comprising:

an array of memory cells formed in rows and columns, wherein each memory cell in the array of memory cells includes;

a pillar extending outwardly from a semiconductor substrate, wherein the pillar includes a single crystalline first contact layer and a single crystalline second contact layer separated by an oxide layer;

a single crystalline vertical transistor formed along alternating sides of the pillar within a row of pillars, wherein the single crystalline vertical transistor includes;

an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;

an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer;

an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions; and

wherein a surface space charge region for the single crystalline vertical transistor scales down as other dimensions of the transistor scale down;

a plurality of buried bit lines formed of single crystalline semiconductor material and disposed below the pillars in the array memory cells for interconnecting with the first contact layer of column adjacent pillars in the array of memory cells; and

a plurality of word lines, each word line disposed orthogonally to the plurality of buried bit lines in a trench between rows of the pillars for addressing alternating body regions of the single crystalline vertical transistors that are adjacent to the trench.

14. A folded bit line DRAM device, comprising:

an array of memory cells formed in rows and columns, wherein each memory cell in the array of memory cells includes;

a pillar extending outwardly from a semiconductor substrate, wherein the pillar includes a single crystalline first contact layer and a single crystalline second contact layer separated by an oxide layer;

a single crystalline vertical transistor formed along alternating sides of the pillar within a row of pillars, wherein the single crystalline vertical transistor includes;

an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;

an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer; and

an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions; and

wherein a horizontal junction depth for the first and the second ultra thin single crystalline vertical source/drain regions is much less than a vertical length of the ultra thin single crystalline vertical body region

a plurality of buried bit lines formed of single crystalline semiconductor material and disposed below the pillars in the array memory cells for interconnecting with the first contact layer of column adjacent pillars in the array of memory cells; and

a plurality of word lines, each word line disposed orthogonally to the plurality of buried bit lines in a trench between rows of the pillars for addressing body regions of the single crystalline vertical transistors that are adjacent to the trench.

15. The folded bit line DRAM device of claim 14, wherein the ultra thin single crystalline vertical body region includes a p-type channel having a vertical length of less than 100 nanometers.

16. A semiconductor device, comprising:

an array of pillars formed in rows and columns extending outwardly from a semiconductor substrate, wherein each pillar includes a single crystalline first contact layer and a single crystalline second contact layer separated by an oxide layer;

a pair of single crystalline vertical transistors formed along opposing sides of each pillar, wherein each single crystalline vertical transistor includes;

an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;

an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer;

an ultra thin single crystalline vertical body region formed along side of the oxide in each pillar and which couples the first and the second source/drain regions formed along side of the pillar

a number of buried bit lines formed of single crystalline semiconductor material and disposed below the single crystalline vertical body regions, wherein the number of buried bit lines couple to the first contact layer along columns of pillars;

a number of wordlines, wherein each wordline is disposed in a trench formed between rows of pillars and below a top surface of the pillars, and wherein each wordline independently addresses body regions for the pair of single crystalline vertical transistors in alternating pillars along a row of pillars; and

a number of capacitors which independently couple to the second contact layer in each pillar.

17. The semiconductor device of claim 16, wherein each wordline integrally forms a gate for addressing the body region in a pillar on a first side of the trench and is isolated from the body region in a column adjacent pillar on a second side of the trench.

18. The semiconductor device of claim 16, wherein each wordline integrally forms a gate for addressing the body region in a pillar on the first side of the trench and is isolated from the body region in a row adjacent pillar on the first side of the trench.

19. The semiconductor device of claim 16, wherein each ultra thin single crystalline vertical body region includes a p-type channel having a vertical length of less than 100 nanometers.

20. The semiconductor device of claim 16, wherein the number of buried bit lines are formed integrally with the first contact layer and are separated from the semiconductor substrate by an oxide layer.

21. The semiconductor device of claim 16, wherein each wordline includes a horizontally oriented wordline having a vertical side length of less than 100 nanometers.

22. The semiconductor device of claim 16, wherein each wordline includes a vertically oriented wordline having a vertical length of less than 100 nanometers.

23. A semiconductor device, comprising:

a folded bit line array of memory cells, wherein each memory cell in the array of memory cells includes;

a pillar extending outwardly from a semiconductor substrate, wherein the pillar includes a single crystalline first contact layer and a single crystalline second contact layer separated by an oxide layer;

a single crystalline vertical transistor formed along alternating sides of the pillar within a row of pillars, wherein the single crystalline vertical transistor includes;

an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;

an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer; and

an ultra thin single crystalline vertical body region formed along side of the oxide layer and which couples the first and the second source/drain regions; and

a gate opposing the vertical body region and separated therefrom by a gate oxide;

a plurality of buried bit lines formed of single crystalline semiconductor material and disposed below the pillars in the array memory cells for interconnecting with the first contact layer of column adjacent pillars in the array of memory cells; and

a plurality of word lines, each word line disposed orthogonally to the plurality of buried bit lines in a trench between rows of the pillars for addressing gates of the single crystalline vertical transistors that are adjacent to the trench in alternating pillars along a row of pillars.

24. The semiconductor device of claim 23, wherein each single crystalline vertical body region includes a p-type channel having a vertical length of less than 100 nanometers.

25. The semiconductor device of claim 23, wherein each of the plurality of buried bit lines is separated by an oxide layer from the semiconductor substrate.

26. The semiconductor device of claim 23, wherein each gate in a trench along a row of pillars is integrally formed with one of the plurality of word lines in the adjacent trench, and wherein each of the plurality of word lines includes a horizontally oriented word line having a vertical side of less than 100 nanometers opposing the single crystalline vertical body regions.

27. The semiconductor device of claim 23, wherein each gate in a trench along a row of pillars is integrally formed with one of the plurality of word lines in the adjacent trench, and wherein each of the plurality of word lines includes a vertically oriented word line having a vertical length of less than 100 nanometers.

28. A memory device, comprising:

an array of memory cells, wherein each memory cell in the array of memory cells includes;

a pillar extending outwardly from a semiconductor substrate, wherein the pillar includes a single crystalline first contact layer and a single crystalline second contact layer separated by an oxide layer;

a single crystalline vertical transistor, wherein the single crystalline vertical transistor includes;

an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;

an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer;

an ultra thin single crystalline vertical body region formed along alternating sides of the pillar within a row of pillars and coupling the first and the second source/drain regions; and

a gate opposing the vertical body region and separated therefrom by a gate oxide;

a plurality of buried bit lines formed of single crystalline semiconductor material and disposed below the pillars in the array memory cells for interconnecting with the first contact layer of column adjacent pillars in the array of memory cells;

a plurality of first word lines, each first word line disposed orthogonally to the plurality of buried bit lines in a trench between rows of the pillars for addressing gates of the single crystalline vertical transistors that are adjacent to a first side of the trench in alternating pillars along the first side of the trench; and

a plurality of second word lines, each second word line disposed orthogonally to the bit lines in the trench between rows of the pillars and separated from each first word line by an insulator such that the second wordline is adjacent a second side of the trench and addresses gates of the single crystalline vertical transistors that are adjacent to a second side of the trench in alternating pillars along a second side of the trench.

29. The memory device of claim 28, wherein each gate adjacent to a first side of the trench along a row of pillars is integrally formed with one of the plurality of first word lines in the adjacent trench, and wherein each of the plurality of first word lines includes a vertically oriented word line having a vertical length of less than 100 nanometers.

30. The memory device of claim 28, wherein each pillar includes a capacitor coupled to the second contact layer.

31. The memory device of claim 28, wherein each single crystalline vertical body region has a vertical length of less than 100 nanometers.

32. The memory device of claim 28, wherein each single crystalline vertical transistors has a vertical length of less than 100 nanometers and a horizontal width of less than 10 nanometers.

33. A memory device, comprising:

a folded bit line array of memory cells, wherein each memory cell in the array of memory cells includes;

a pillar extending outwardly from a semiconductor substrate, wherein the pillar includes a single crystalline first contact layer and a single crystalline second contact layer separated by an oxide layer;

a pair of single crystalline vertical transistors formed along opposing sides of each pillar, wherein each single crystalline vertical transistor includes;

an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;

an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer; and

an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions;

a plurality of buried bit lines formed of single crystalline semiconductor material and disposed below the pillars in the array memory cells for interconnecting with the first contact layer of column adjacent pillars in the array of memory cells; and

a plurality of first word lines, each first word line disposed orthogonally to the plurality of buried bit lines in a trench between rows of the pillars for addressing body regions of the single crystalline vertical transistors in alternating row adjacent pillars that are adjacent to a first side of the trench; and

a plurality of second word lines, each second word line disposed orthogonally to the bit lines in the trench between rows of the pillars and separated from each first word line by an insulator such that the second wordline is adjacent a second side of the trench and addresses body regions of the single crystalline vertical transistors in alternating row adjacent pillars that are adjacent to a second side of the trench.

34. The memory device of claim 33, wherein each of the plurality of first wordlines integrally forms a gate for addressing the body region in a pillar on a first side of the trench and is isolated by an insulator layer from the body region in a row adjacent pillar on the first side of the trench.

35. The memory device of claim 33, wherein each of the plurality of second wordlines integrally forms a gate for addressing the body region in a pillar on a second side of the trench and is isolated by an insulator layer from the body region in a row adjacent pillar on the second side of the trench.

36. The memory device of claim 33, wherein each of the plurality of first and second word lines includes a vertically oriented word line having a vertical length of less than 100 nanometers.

37. The memory device of claim 33, wherein each single crystalline vertical transistors has a vertical length of less than 100 nanometers and a horizontal width of less than 10 nanometers.

38. An electronic system, comprising:

a processor; and

a folded bit line DRAM device coupled to the processor, wherein the folded bit line DRAM device includes;

an array of memory cells formed in rows and columns, wherein each memory cell in the array of memory cells includes;

a pillar extending outwardly from a semiconductor substrate, wherein the pillar includes a single crystalline first contact layer and a single crystalline second contact layer separated by an oxide layer;

a single crystalline vertical transistor formed along alternating sides of the pillar within a row of pillars, wherein the single crystalline vertical transistor includes;

an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;

an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer;

an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions; and

wherein a surface space charge region for the single crystalline vertical transistor scales down as other dimensions of the transistor scale down;

a plurality of buried bit lines formed of single crystalline semiconductor material and disposed below the pillars in the array memory cells for interconnecting with the first contact layer of column adjacent pillars in the array of memory cells; and

a plurality of word lines, each word line disposed orthogonally to the plurality of buried bit lines in a trench between rows of the pillars for addressing alternating body regions of the single crystalline vertical transistors that are adjacent to the trench.

39. A method for forming a folded bit line DRAM device, comprising:

forming an array of memory cells formed in rows and columns, wherein forming each memory cell includes;

forming a pillar extending outwardly from a semiconductor substrate, wherein forming the pillar includes forming a single crystalline first contact layer of a first conductivity type and forming a single crystalline second contact layer of the first conductivity type vertically separated by an oxide layer;

forming a single crystalline vertical transistor along alternating sides of the pillar within a row of pillars, and wherein forming the single crystalline vertical transistor includes;

depositing a lightly doped polysilicon layer of a second conductivity type over the pillar and directionally etching the polysilicon layer of the second conductivity type to leave only on sidewalls of the pillars;

annealing the pillar such that the lightly doped polysilicon layer of the second conductivity type recrystallizes and lateral epitaxial solid phase regrowth occurs vertically to form a single crystalline vertically oriented material of the second conductivity type; and

wherein the annealing causes the single crystalline first and second contact layers of a first conductivity type seed a growth of single crystalline material of the first conductivity type into the lightly doped polysilicon layer of the second type to form vertically oriented first and second source/drain regions of the first conductivity type separated by the now single crystalline vertically oriented material of the second conductivity type;

forming a plurality of buried bit lines formed of single crystalline semiconductor material and disposed below the pillars in the array of memory cells, wherein forming the plurality of buried bit lines includes coupling the first contact layer of column adjacent pillars in the array of memory cells; and

forming a plurality of word lines, wherein forming the plurality of word lines includes forming each word line disposed orthogonally to the plurality of buried bit lines in a trench between rows of the pillars for addressing alternating body regions of the single crystalline vertical transistors that are adjacent to the trench.

40. The method of claim 39, wherein forming a single crystalline vertical transistor along alternating sides of the pillar within a row of pillars includes forming the transistor such that the transistor has an ultra thin single crystalline vertical body region having a horizontal width of less than 10 nanometers.

41. The method of claim 39, wherein forming a single crystalline vertical transistor along alternating sides of the pillar within a row of pillars includes forming the transistor such that the transistor has a vertical channel length of less than 100 nanometers and has a first and a second source/drain regions wherein the first and the second source/drain regions have a horizontal width of less than 10 nanometers.

42. A method for forming a folded bit line DRAM device, comprising:

forming an array of memory cells formed in rows and columns, wherein forming each memory cell in the array of memory cells includes;

forming a pillar extending outwardly from a semiconductor substrate, wherein the pillar includes a single crystalline first contact layer and a single crystalline second contact layer separated by an oxide layer;

forming a single crystalline vertical transistor along alternating sides of the pillar within a row of pillars, wherein forming the single crystalline vertical transistor includes;

forming an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;

forming an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer;

forming an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions; and

wherein forming the single crystalline vertical transistor includes forming the transistor such that a surface space charge region for the single crystalline vertical transistor scales down as other dimensions of the transistor scale down;

forming a plurality of buried bit lines formed of single crystalline semiconductor material and disposed below the pillars in the array memory cells, wherein forming the plurality of buried bit lines includes coupling the first contact layer of column adjacent pillars in the array of memory cells memory cells; and

forming a plurality of word lines, wherein forming the plurality of word lines includes forming each word line disposed orthogonally to the plurality of buried bit lines in a trench between rows of the pillars for addressing alternating body regions of the single crystalline vertical transistors that are adjacent to the trench.

43. The method of claim 42, wherein forming the plurality of buried bit lines includes forming a plurality of buried bit lines which are more heavily doped than the first contact layer and are formed integrally with the first contact layer.

44. The method of claim 42, wherein forming a single crystalline vertical transistor along alternating sides of the pillar within a row of pillars includes forming the transistor such that the transistor has the ultra thin single crystalline vertical body region with a p-type channel having a vertical length of less than 100 nanometers.

45. The method of claim 44, wherein forming the transistor such that the transistor has the ultra thin single crystalline vertical body region includes forming the ultra thin single crystalline vertical body region to have a horizontal width of less than 10 nanometers

46. The method of claim 42, wherein forming a plurality of buried bit lines of single crystalline semiconductor material below the pillar includes forming a pluraltiy of buried bit lines which are separated from the semiconductor substrate by an insulator layer.

47. The method of claim 42, wherein forming the plurality of wordlines includes integrally forming a horizontally oriented gate for addressing alternating body regions of the single crystalline vertical transistors that are adjacent to the trench, wherein a vertical side of the horizontally oriented gate has a length of less than 100 nanometers.

48. The method of claim 42, wherein forming the plurality of wordlines includes integrally forming a vertically oriented gate for addressing alternating body regions of the single crystalline vertical transistors in a row of pillars that are adjacent to the trench, wherein the integrally formed vertically oriented gate has a vertical length of less than 100 nanometers.

49. A method for forming a memory array, comprising:

forming a folded bit line array of memory cells, wherein forming each memory cell in the array of memory cells includes;

forming a pillar, extending outwardly from a semiconductor substrate, wherein forming the pillar includes forming a single crystalline first contact layer of a first conductivity type and forming a single crystalline second contact layer of the first conductivity type vertically separated by an oxide layer;

forming a single crystalline vertical transistor along alternating sides of the pillar within a row of pillars, wherein forming the single crystalline vertical transistor includes;

depositing a lightly doped polysilicon layer of a second conductivity type over the pillar and directionally etching the polysilicon layer of the second conductivity type to leave only on sidewalls of the pillars;

annealing the pillar such that the lightly doped polysilicon layer of the second conductivity type recrystallizes and lateral epitaxial solid phase regrowth occurs vertically to form a single crystalline vertically oriented material of the second conductivity type; and

wherein the annealing causes the single crystalline first and second contact layers of a first conductivity type seed a growth of single crystalline material of the first conductivity type into the lightly doped polysilicon layer of the second type to form vertically oriented first and second source/drain regions of the first conductivity type separated by the now single crystalline vertically oriented material of the second conductivity type; and

forming a gate opposing the single crystalline vertically oriented material of the second conductivity type and separated therefrom by a gate oxide;

forming a plurality of buried bit lines of single crystalline semiconductor material and disposed below the pillars in the array memory cells such that each one of the plurality of buried bit lines couples the first contact layer of column adjacent pillars in the array of memory cells; and

forming a plurality of word lines disposed orthogonally to the plurality of buried bit lines, wherein forming the plurality of word lines includes forming each one of the plurality of wordlines in a trench between rows of the pillars for addressing gates of the single crystalline vertical transistors that are adjacent to the trench.

50. The method of claim 49, wherein forming each single crystalline vertical transistor includes forming an ultra thin body region with a p-type channel having a vertical length of less than 100 nanometers and a horizontal width of less than 10 nanometers.

51. The method of claim 49, wherein forming the plurality of buried bit lines includes forming the plurality of buried bit lines separated by an oxide layer from the semiconductor substrate.

52. The method of claim 49, wherein forming the plurality of wordlines includes integrally forming each gate, present in the adjacent trench along alternating pillars along a row of pillars, with one of the plurality of word lines, and wherein forming each of the plurality of word lines includes forming a horizontally oriented word line having a vertical side of less than 100 nanometers opposing the single crystalline vertical transistor.

53. The method of claim 49, wherein forming the plurality of wordlines includes integrally forming, present in the adjacent trench along alternating pillars along a row of pillars, with one of the plurality of word lines, and wherein forming each of the plurality of word lines includes forming a vertically oriented word line having a vertical length of less than 100 nanometers.

54. A method of forming a memory device, comprising:

forming an array of memory cells, wherein forming each memory cell in the array of memory cells includes;

forming a pillar extending outwardly from a semiconductor substrate, wherein forming the pillar includes forming a single crystalline first contact layer of a first conductivity type and forming a single crystalline second contact layer of the first conductivity type vertically separated by an oxide layer;

forming a pair of single crystalline vertical transistor along opposing sides of the pillar, wherein forming each one of the pair of single crystalline vertical transistors includes;

depositing a lightly doped polysilicon layer of a second conductivity type over the pillar and directionally etching the polysilicon layer of the second conductivity type to leave only on opposing sidewalls of the pillars;

annealing the pillar such that the lightly doped polysilicon layer of the second conductivity type recrystallizes and lateral epitaxial solid phase regrowth occurs vertically to form a single crystalline vertically oriented material of the second conductivity type; and

wherein the annealing causes the single crystalline first and second contact layers of a first conductivity type seed a growth of single crystalline material of the first conductivity type into the lightly doped polysilicon layer of the second type to form vertically oriented first and second source/drain regions of the first conductivity type separated by the now single crystalline vertically oriented material of the second conductivity type; and

forming a pair of gates, each gate opposing the single crystalline vertically oriented material of the second conductivity type and separated therefrom by a gate oxide;

forming a plurality of buried bit lines of single crystalline semiconductor material and disposed below the pillars in the array memory cells such that each one of the plurality of buried bit lines couples the first contact layer of column adjacent pillars in the array of memory cells; and

forming a plurality of first word lines disposed orthogonally to the plurality of buried bit lines in a trench between rows of the pillars for addressing gates of the single crystalline vertical transistors that are adjacent to a first side of the trench in alternating pillars along the first side of the trench; and

forming a plurality of second word lines disposed orthogonally to the bit lines in the trench between rows of the pillars and separated from each first word line by an insulator such that the second wordline is adjacent a second side of the trench and addresses gates of the single crystalline vertical transistors that are adjacent to a second side of the trench in alternating pillars along the second side of the trench.

55. The method of claim 54, wherein forming the plurality of first and second wordlines includes integrally forming each gate in alternating pillars along a row of pillars adjacent the first and the second side of the trench respectively with one of the plurality of the first and the second word lines, and isolating the plurality of first and second wordlines adjacent the first side and the second side of the trench respectively from the gates in row adjacent pillars.

56. The method of claim 55, wherein forming each of the plurality of first and second word lines includes forming vertically oriented word lines having a vertical length of less than 100 nanometers.

57. The method of claim 54, wherein forming each single crystalline vertical transistor includes forming the single crystalline vertical transistor to have a vertical length of less than 100 nanometers and a horizontal width of less than 10 nanometers.

58. The method of claim 54, wherein forming each single crystalline vertical transistor includes forming the single crystalline vertical transistor such that a horizontal junction depth for the first and the second source/drain regions first conductivity type is much less than a vertical length of the single crystalline vertically oriented material of the second conductivity type.

59. The method of claim 54, wherein forming each single crystalline vertical transistor includes forming the single crystalline vertical transistor such that a surface space charge region for the single crystalline vertical transistor scales down as other dimensions of the transistor scale down.