MULTI-PHASE DC-TO-DC BUCK CONVERTER WITH MULTI-PHASE CURRENT BALANCE AND ADJUSTABLE LOAD REGULATION

• US 20040008011A1
• Filed: 07/12/2002
• Published: 01/15/2004
• Est. Priority Date: 07/12/2002
• Status: Active Grant

• Current Assignee: Richtek Technology Corporation (MediaTek, Inc.)
• Original Assignee: Richtek Technology Corporation (MediaTek, Inc.)
• Inventors: Liu, Jing-Meng, Tai, Liang-Pin, Wang, Hung-I, Hsieh, Shwu-Liang
• Granted Patent: US 6,670,794 B1
• Time in Patent Office: Days
• US Class Current: 323/213
• CPC Class Codes: H02M 3/1584 with a plurality of power processing stages connected in parallel

Abstract

To balance the current of individual channel as well as regulate the output voltage for a multi-phase DC-to-DC buck converter, the converter output voltage is sensed and compared with a reference signal to produce a first error signal serving as first control signal for PWM signals of the converter and the channel currents are sensed, summed, averaged and subtracted to produce second error signals that are further modified by saw-tooth wave signal to produce second control signals for the PWM signals. Moreover, the reference signal is controlled by the summed channel currents for adjustable load regulation.

Claims

1. A multi-phase DC-to-DC buck converter for transforming a supply voltage to a converter output voltage by splitting an input current to a plurality of channel currents, said converter comprising:

a voltage sense circuit for sensing said converter output voltage and generating a first sense signal;

a plurality of current sense circuits each for sensing a respective one of said plurality of channel currents and generating a respective second sense signal;

an error amplifier for comparing said first sense signal with a reference signal and generating a first error signal serving as a first control signal;

a first summing circuit for summing said plurality of second sense signals and generating a summed signal;

an averaging circuit for averaging said summed signal and generating an average signal;

a plurality of subtracting circuits each for subtracting said average signal from one of said plurality of second sense signals and generating a respective second error signal;

a plurality of second summing circuits each for adding one of said plurality of second error signals to a respective ramp signal and generating a respective second control signal; and

a plurality of PWM comparators each for receiving said first control signal and one of plurality of second control signals and generating a PWM signal for regulating said channel current of said corresponding channel.

2. A converter according to claim 1 wherein said current sense circuit comprises:

a current sense resistor for producing a sensed voltage responsive to said channel current of said corresponding channel;

a differential input GM amplifier for transforming said sensed voltage to a current sense signal; and

a sampling and holding circuit for transforming said current sense signal to said second sense signal.

3. A converter according to claim 1 further comprising a regulator for producing said reference signal under control of said summed signal.

4. A converter according to claim 3 wherein said regulator comprises:

an adjustable resistor for transforming said summed signal to a load regulation voltage signal;

a high-impedance unit gain buffer for transforming said load regulation voltage signal to a reference voltage drop;

means for producing an intermediate voltage in proportional to said reference voltage drop; and

means for subtracting said intermediate voltage from a second supply voltage to produce said reference signal.

5. A method for balancing a plurality of channel currents in a multi-phase DC-to-DC buck converter transforming a supply voltage to a converter output voltage by splitting an input current to said plurality of channel currents, said method comprising the steps of:

sensing said converter output voltage to thereby determine a first sense signal;

sensing each of said plurality of channel currents to thereby determine a plurality of second sense signals;

comparing said first sense signal with a reference signal to thereby determine a first error signal serving as a first control signal;

summing said plurality of second sense signals to thereby determine a summed signal;

averaging said summed signal to thereby determine an average signal;

subtracting said average signal from each of said plurality of second sense signals to thereby determine a plurality of second error signals;

adding each of said plurality of second error signals to a respective ramp signal to thereby determine a plurality of second control signals;

generating a plurality of PWM signals by a plurality of PWM comparators each comparing said first control signal with one of said plurality of second control signals; and

regulating said plurality of channel currents with said plurality of PWM signals.

6. A method according to claim 5 wherein said second control signal is obtained by shifting a DC offset of said ramp signal.

7. A method according to claim 5 wherein said second control signal is obtained by scaling an amplitude of said ramp signal.

8. A method according to claim 5 further comprising regulating said reference signal under control of said summed signal.