Liquid crystal display

• US 20040008292A1
• Filed: 01/27/2003
• Published: 01/15/2004
• Est. Priority Date: 07/27/2000
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Dong-Gyu Kim, Sang-Soo Kim, Sang-Wook Lee
• Inventors: Kim, Sang-Soo, Kim, Dong-Gyu, Lee, Sang-Wook
• Granted Patent: US 6,741,309 B2
• Time in Patent Office: Days
• US Class Current: 349/43
• CPC Class Codes: G02F 1/1345 Conductors connecting electrodes to cell terminals
• CPC Class Codes: G02F 1/13452 Conductors connecting driver circuitry and terminals of panels
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line

Abstract

A liquid crystal display includes an insulating substrate, gate and data lines formed on the substrate to define pixel areas, or collectively a display area. Gate signal interconnection wires are formed at a corner portion of the substrate outside the display area to transmit gate electrical signals, and provided with gate signal interconnection lines and first and second gate signal interconnection pads connected to both ends of the gate signal interconnection lines. A gate insulating layer, and a protective layer are further formed on the substrate, and provided with first and second contact holes exposing the first and second gate signal interconnection pads. Gate and data signal transmission films are attached to the substrate, and provided with first and second gate signal leads and first and second gate signal wires. The first and second gate signal leads are connected to the first and second gate signal interconnection pads through the first and second contact holes. The first or the second gate signal lead completely covers the first or the second contact hole at least in the longitudinal direction of the lead.

Claims

1. A liquid crystal display, comprising:

an insulating substrate having a plurality of gate lines, a plurality of data lines crossing over the gate lines to define pixel areas, a gate signal interconnection line assembly with gate signal interconnection lines and first and second gate signal interconnection pads connected to both ends of the gate signal interconnection lines to relay gate electrical signals to the gate lines, and insulating layers with first and second contact holes exposing the first and second gate signal interconnection pads;

gate signal transmission films attached to the substrate while each mounting a gate driving integrated circuit thereon to receive gate electrical signals and send gate signals to the gate lines, each gate transmission film having first gate signal wires, and first gate signal leads connected to the first gate signal interconnection pads through the first contact holes; and

signal transmission films attached to the substrate with second gate signal wires, and second gate signal leads connected to the second gate signal interconnection pads through the second contact holes;

wherein the first or the second gate signal lead completely covers the first or the second contact hole at least in the longitudinal direction of the lead.

2. The liquid crystal display of claim 1, further comprising pixel electrodes formed on the insulating layer at the pixel areas.

3. The liquid crystal display of claim 2, further comprising first and second subsidiary gate signal interconnection pads formed at the same plane as the pixel electrodes while covering the first and second contact holes, the first and second subsidiary gate signal interconnection pads positioned between the first and second gate signal interconnection pads and the first and second gate signal leads, respectively.

4. The liquid crystal display of claim 1, wherein the insulating layers comprise a gate insulating layer covering the gate lines, and a protective layer covering the data lines over the gate insulating layer.

5. The liquid crystal display of claim 1, wherein the first or the second gate signal lead completely covers at least one side of each contact hole in the longitudinal direction.

6. The liquid crystal display of claim 4, wherein the gate signal interconnection line assembly is formed at the same plane as the gate lines, and the first and second contact holes are formed at both of the gate insulating layer and the protective layer.

7. The liquid crystal display of claim 4, wherein the gate signal interconnection line assembly is formed at the same plane as the data lines, and the first and second contact holes are formed only at the protective layer.

8. The liquid crystal display of claim 3, wherein the gate signal interconnection line assembly comprises first gate signal interconnection lines formed at the same plane as the gate lines, and second gate signal interconnection lines formed at the same plane as the data lines.

9. The liquid crystal display of claim 8, wherein the first and the second gate signal interconnection lines are connected to each other via the first and second subsidiary gate signal interconnection pads.

10. The liquid crystal display of claim 1, wherein the signal transmission films are data signal transmission films each mounted with a data driving integrated circuit to receive data electrical signals and send data signals to the data lines.

11. The liquid crystal display of claim 10, further comprising a printed circuit board connected to the data signal transmission films to send the gate and data electrical signals to the gate driving integrated circuits and the data driving integrated circuit.

12. A liquid crystal display, comprising:

an insulating substrate having a plurality of gate lines, a plurality of data lines crossing over the gate lines to define pixel areas, a gate signal interconnection line assembly with gate signal interconnection lines and first and second gate signal interconnection pads formed at both ends of the gate interconnection lines, and insulating layers with first and second contact holes exposing the first and second gate signal interconnection pads;

wherein the first and second gate signal interconnection pads are formed at the same plane as the data lines.

13. The liquid crystal display of claim 12, further comprising pixel electrodes formed on the insulating layer at the pixel areas.

14. The liquid crystal display of claim 13, further comprising first and second subsidiary gate signal interconnection pads formed at the same plane as the pixel electrodes while covering the first and second contact holes, the first and second subsidiary gate signal interconnection pads being positioned between the first and second gate signal interconnection pads and the first and second gate signal leads, respectively.

15. The liquid crystal display of claim 12, wherein the insulating layers comprise a gate insulating layer covering the gate lines, and a protective layer comprising the data lines over the gate insulating layer.

16. The liquid crystal display of claim 12, further comprising gate signal transmission films attached to the substrate while each mounting a gate driving integrated circuit to receive gate electrical signals and send gate signals to the gate lines, each gate signal transmission film having first gate signal wires, and first gate signal leads connected to the first gate signal interconnection pads through the first contact holes.

17. The liquid crystal display of claim 12, further comprising data signal transmission films attached to the substrate while each mounting a data driving integrated circuit to receive data electrical signals and send data signals to the data lines, the data signal transmission film having second gate signal wires, and second gate signal leads connected to the second gate signal interconnection pads through the second contact holes.