Multiple use memory chip

• US 20040008541A1
• Filed: 07/10/2002
• Published: 01/15/2004
• Est. Priority Date: 07/10/2002
• Status: Active Grant

• Current Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Eitan, Boaz, Maayan, Eduardo
• Granted Patent: US 6,917,544 B2
• Time in Patent Office: Days
• US Class Current: 365/185.33
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data

Abstract

A die for a memory array may store Flash and EEPROM bits in at least one Nitride Read Only Memory (NROM) array. Each array may store Flash, EEPROM or both types of bits.

Claims

1. A die comprising:

at least one flash array; and

at least one electrically erasable, programmable read only memory (EEPROM) array,

wherein both types of arrays are manufactured with generally the same process steps.

2. The die according to claim 1 wherein both said flash and EEPROM arrays are virtual ground segmented arrays.

3. The die according to claim 2 wherein at least at least one of said arrays comprises word lines and bit lines, isolation columns between groups of bit lines and select transistors between groups of word lines.

4. The die according to claim 3 and wherein said isolation column is formed from a thick oxide region.

5. The die according to claim 3 and wherein said isolation column is formed from a non-used column of memory cells.

6. The die according to claim 2 wherein said arrays comprise word lines and bit lines organized into blocks, wherein the bits of a block of said at least one flash array are group erasable and wherein at least one bit of a block of said at least one EEPROM array is individually erasable.

7. The die according to claim 6 wherein said individually erasable bits are directly erasable without a need to emulate the EEPROM functionality.

8. The die according to claim 1 and wherein both said flash and EEPROM arrays comprise virtual ground array isolated slices.

9. The die according to claim 8 and wherein said slices are of generally the same length and width.

10. The die according to claim 8 and wherein said slices are of different lengths and/or widths.

11. The die according to claim 8 wherein at least one of said arrays comprises slices with multiple lengths and/or widths.

12. The die according to claim 1 wherein said at least one flash array is a virtual ground segmented array and said at least one EEPROM array is a NOR-type segmented array.

13. The die according to claim 1 wherein said at least one flash array has flash memory cells and said at least one EEPROM array has EEPROM memory cells and wherein said flash and EEPROM memory cells are nitride read only memory (NROM) cells.

14. The die according to claim 13 and wherein said NROM cells comprise two separated storage areas.

15. The die according to claim 14 and wherein each of said storage areas is adapted to store one or more bits of data.

16. The die according to claim 13 and wherein said NROM cells comprise one storage area.

17. The die according to claim 14 and wherein each said storage area is adapted to store one or more bits of data.

18. The die according to claim 13 and wherein said NROM cells of one array store data in one storage area within each cell and the NROM cells of the other array store data in two storage areas within each cell.

19. The die according to claim 18 and wherein each storage area in a cell may store one or more bits of data.

20. The die according to claim 13 and wherein said NROM cells in each array have substantially the same structure.

27. The die according to any of claims 1-23 and wherein said at least one EEPROM array does not have one select element per each memory cell.

21. Flash and EEPROM arrays on a single die where either one of the arrays can be operated at any time.

22. A die comprising:

at least one flash array; and

at least one EEPROM array,

wherein both arrays can be operated at the same time.

23. A die comprising:

at least one flash array; and

at least one EEPROM array,

wherein substantially the same peripheral circuits are used to operate all of said arrays.

24. A non-volatile memory array wherein part of the array is operated as a flash array and another part of the array is operated as an EEPROM array.

25. The array according to claim 24 and wherein which memory cells operate as flash cells and which memory cells operate as EEPROM cells is predetermined.

26. The array according to claim 24 and wherein which memory cells operate as flash cells and which memory cells operate as EEPROM cells is determined by a user.

28. The array according to any of claims 24-26 and wherein said at least one EEPROM array does not have one select element per each memory cell.

29. The array according to any of claims 24-26 and wherein said at least one EEPROM array does not have one select element per each memory cell.

30. A die comprising:

a plurality of Flash bits;

a plurality of EEPROM bits,

said bits stored in at least one memory array having NROM memory cells,

wherein each said memory array stores bits of one of the following types;

Flash, EEPROM, or both.

31. The die according to claim 30 and wherein at least one of said at least one array is a NOR array.

32. The die according to claim 30 and wherein at least one of said at least one memory array is a virtual ground array.

33. The die according to claim 30 in which the EEPROM and Flash bits share the same word lines.

34. The die according to claim 30 in which the EEPROM and Flash bits share the same global bit lines.

35. The die according to 30 wherein said at least one memory array comprises more than one type of Flash arrays and more than one type of EEPROM array.

36. The die according to claim 35 wherein the type of array is defined by any of the following:

the granularity of operation, burst operation, the programming rate, and the erase granularity.

37. The die according to 30 wherein said at least one memory array has word lines for Flash bits and word lines for EEPROM bits.