DSO timing source transient compensation

• US 20040008696A1
• Filed: 04/15/2002
• Published: 01/15/2004
• Est. Priority Date: 04/15/2002
• Status: Active Grant

• Current Assignee: WSOU Investments, LLC (WSOU Holdings, LLC)
• Original Assignee: Alcatel SA (Nokia Corporation)
• Inventors: Gammenthaler, Robert S. Jr., Marcoux, Matthew J.
• Granted Patent: US 7,209,492 B2
• Time in Patent Office: Days
• US Class Current: 370/395.62
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H04J 3/0688 Change of the master or reference, e.g. take-over or failure of the master

Abstract

System and method for compensating for DS0 timing source transients, such as may occur during a switchover to a new external reference, is described. In one embodiment, an SFI control signal is monitored for embedded frame position information. When the frame position information is initially detected, a 10-bit frame clock counter is reset to zero. The counter is then incremented using an 8.192 MHz clock. From that point on, each time the SFI frame position information is detected, the value of the frame clock counter is checked. If the counter value is zero, the counter continues to run freely. If the counter value is non-zero and the most significant bit (“MSB”) thereof is zero, the count of the frame clock counter is held for one clock period. If the counter value is non-zero and the MSB thereof is one, the count of the frame clock counter is advanced by a value of two, rather than one, for one clock period.

Claims

1. A method of compensating for timing source transients caused by misalignment of first and second clock signals, the method comprising the steps of:

monitoring a control signal transmitted using the second clock signal for frame position information for the first clock signal;

responsive to detection of frame position information, determining whether the first and second clock signals are misaligned; and

responsive to a determination that the first and second signals are misaligned, periodically temporarily altering one clock period of the first clock signal until the first and second signals are realigned.

2. The method of claim 1 wherein the periodically temporarily altering one clock period comprises the step of stretching the clock period.

3. The method of claim 1 wherein the periodically temporarily altering one clock period comprises the step of contracting the clock period.

4. A method of compensating for timing source transients caused by misalignment of first and second clock signals, the method comprising the steps of:

monitoring a control signal transmitted using the second clock signal for frame position information for the first clock signal;

responsive to detection of frame position information, resetting a counter to zero;

causing the counter to increment using the first clock signal;

continuing to monitor the control signal for frame position information;

responsive to each subsequent detection of frame position information;

determining a value of the counter;

if the value of the counter is non-zero and the most significant bit (“

MSB”

) of the counter is zero, advancing the value of the counter by more than one count for one clock cycle; and

if the value of the counter is non-zero and the MSB of the counter is non-zero, holding the value of the counter for at least one clock cycle.

5. The method of claim 4 wherein the counter is a 10-bit counter.

6. The method of claim 4 wherein the first clock signal is an 8.192 MHz clock signal.

7. The method of claim 4 wherein the second clock signal is a 19.44 MHz clock signal.

8. The method of claim 4 wherein the control signal is a serially encoded super frame indicator (“

SFI”

) signal for use in a telecommunications signaling server.

9. The method of claim 4 further comprising the steps of:

using the second least significant bit of the counter to generate a third clock signal; and

using the third clock signal to transmit DS0 data to and from a DS0 interface module.

10. The method of claim 4 wherein the frame position information indicates a position of an 8 KHz frame position relative to a sync pattern of the control signal.

11. A system for compensating for timing source transients caused by misalignment of first and second clock signals, the system comprising:

means for monitoring a control signal transmitted using the second clock signal for frame position information for the first clock signal;

means responsive to detection of frame position information for resetting a counter to zero;

means for causing the counter to increment using the first clock signal;

means for continuing to monitor the control signal for frame position information;

means responsive to each subsequent detection of frame position information for determining a value of the counter;

means responsive to a determination that the value of the counter is non-zero and the most significant bit (“

MSB”

) of the counter is zero for advancing the value of the counter by more than one count for one clock cycle; and

means responsive to a determination that the value of the counter is non-zero and the MSB of the counter is non-zero for holding the value of the counter for at least one clock cycle.

12. The system of claim 11 wherein the first clock signal is an 8.192 MHz clock signal.

13. The system of claim 11 wherein the second clock signal is a 19.44 MHz clock signal.

14. The system of claim 13 wherein the control signal is a serially encoded super frame indicator (“

SFI”

) signal for use in a telecommunications signaling server.

15. The system of claim 13 further comprising:

means for using the second least significant bit of the counter to generate a third clock signal; and

means for using the third clock signal to transmit DS0 data to and from a DS0 interface module.

16. The system of claim 13 wherein the counter is a 10-bit counter.

17. The system of claim 13 wherein the frame position information indicates a position of an 8 KHz frame position relative to a sync pattern of the control signal.

18. Apparatus for compensating for timing source transients caused by misalignment of first and second clock signals in a telecommunications signaling server, the apparatus comprising:

logic for monitoring a control signal transmitted using the second clock signal for frame position information for the first clock signal;

a counter connected to the monitoring logic;

logic responsive to detection of frame position information for resetting the counter to zero;

wherein, subsequent to the resetting, the counter increments using the first clock signal;

wherein the monitoring logic continues to monitor the control signal for frame position information; and

wherein responsive to each subsequent detection of frame position information by the monitoring logic, the monitoring logic determines a value of the counter and, if the value of the counter is non-zero and the most significant bit (“

MSB”

) of the counter is zero, the value of the counter is advanced by more than one count for one clock cycle, and, if the value of the counter is non-zero and the MSB of the counter is non-zero, the value of the counter is held for at least one clock cycle.

19. The apparatus of claim 18 wherein the first clock signal is an 8.192 MHz clock signal.

20. The apparatus of claim 18 wherein the second clock signal is a 19.44 MHz clock signal.

21. The apparatus of claim 18 wherein the control signal is a serially encoded super frame indicator (“

SFI”

) signal for use in a telecommunications signaling server.

22. The apparatus of claim 18 wherein the third least significant bit of the counter is used to generate a third clock signal used to transmit DS0 data to and from a DS0 interface module.

23. The apparatus of claim 18 wherein the frame position information indicates a position of an 8 KHz frame position relative to a sync pattern of the control signal.