Overhead engine for telecommunications nodes

• US 20040008708A1
• Filed: 07/11/2002
• Published: 01/15/2004
• Est. Priority Date: 07/11/2002
• Status: Abandoned Application

• Current Assignee: Bay Microsystems, Inc. (Vcinity, Inc.)
• Original Assignee: Bay Microsystems, Inc. (Vcinity, Inc.)
• Inventors: Giacomini, Peter J.
• Application Number:
  US10/193,579
• Publication Number:
  US 20040008708A1
• Time in Patent Office: Days
• US Class Current: 370/412
• CPC Class Codes: H04J 2203/0021 Control mechanisms
• CPC Class Codes: H04J 2203/0025 Peripheral units
• CPC Class Codes: H04J 3/1611 Synchronous digital hierarchy [SDH] or SONET H04J3/1664 takes precedence for interactions with OTN

Abstract

A novel overhead engine for processing overhead blocks (e.g., SONET/SDH overhead rows of 3 bytes, etc.) in a telecommunications node is disclosed. Some embodiments of the present invention advantageously employ a single instance of logic to process overhead blocks for all of a node'"'"'s input ports. The illustrative embodiment comprises a plurality of multiport cell processors for generating output overhead cells based on input overhead cells, a dispatcher for dispatching input overhead cells to the multiport cell processors, a plurality of aggregators for combining output overhead cells into output overhead blocks, and a scheduler for controlling the order in which output overhead blocks are sent to output processors associated with a node'"'"'s output ports.

Claims

1. An overhead engine in a node of a telecommunication network, said node having at least one input port and at least one output port, said overhead engine comprising:

a dispatcher for

receiving input overhead cells, wherein each of said input overhead cells is associated with a respective one of said input ports, and

routing each of said input overhead cells to a non-empty subset of K multiport cell processors M₁ through M_K, wherein at least one of said multiport cell processors generates an output overhead cell based on at least one of said input overhead cells;

R aggregators A₁ through A_R, wherein each of said aggregators receives at least one of said output overhead cells and generates at least one output overhead block based on said output overhead cells, wherein each of said output overhead blocks is associated with a respective one of said output ports; and

a scheduler for controlling said output ports'"'"' receiving of said overhead blocks from said aggregators;

wherein k and r are positive integers.

2. The overhead engine of claim 1 wherein each of said input overhead cells and each of said output overhead cells belongs to one of K categories C₁ through C_K, and wherein for all i ε

{1,2, . . . , K} said dispatcher dispatches each of said input overhead cells belonging to said category C_i to said multiport cell processor M_l.

3. The overhead engine of claim 1 wherein at least one of said multiport cell processors generates at least one data output and sends said data output to at least one other of said multiport cell processors.

4. The overhead engine of claim 3 wherein said other multiport cell processor uses said data output to determine said other multiport cell processor'"'"'s state.

5. The overhead engine of claim 3 wherein said other multiport cell processor generates at least one said output overhead cell based on said data output.

6. The overhead engine of claim 1 wherein at least one of said multiport cell processors generates an error interrupt.

7. The overhead engine of claim 1 further comprising K buffers, wherein each of said K buffers is associated with a respective one of said K multiport cell processors, and wherein said dispatcher dispatches said input overhead blocks to each of said K multiport cell processors via said associated buffer.

8. A node in a telecommunication network, said node having at least one input port and at least one output port, said node comprising:

a switch;

an overhead engine for generating at least one output overhead cell based on at least one input overhead cell;

at least one input processor for

receiving input frames from a respective one of said input ports, wherein each of said input frames comprises a data portion and at least one of said input overhead cells,

transmitting said data portions to said switch, and

transmitting said input overhead cells to said overhead engine; and

at least one output processor for

receiving at least one of said data portions from said switch,

receiving at least one of said output overhead cells from said overhead engine,

building an output frame comprising at least one of said data portions and at least one of said output overhead cells, and

outputting said output frame on a respective one of said output ports;

wherein said overhead engine is CHARACTERIZED BY;

a dispatcher for

receiving said input overhead cells, wherein each of said input overhead cells is associated with a respective one of said input ports, and

routing each of said input overhead cells to a non-empty subset of K multiport cell processors M₁ through M_K, wherein at least one of said multiport cell processors generates at least one of said output overhead cells based on at least one of said input overhead cells;

R aggregators A₁ through A_R, wherein each of said aggregators receives at least one of said output overhead cells and generates at least one output overhead block based on said output overhead cells, wherein each of said output overhead blocks is associated with a respective one of said output ports; and

a scheduler for controlling said output ports'"'"' receiving of said overhead blocks from said aggregators;

wherein K and R are positive integers.

9. The node of claim 8 wherein each of said input overhead cells and each of said output overhead cells belongs to one of K categories C₁ through C_K, and wherein for all i ε

{1,2, . . . ,K} said dispatcher dispatches each of said input overhead cells belonging to said category C₁ to said multiport cell processor M₁.

10. The node of claim 8 wherein at least one of said multiport cell processors generates at least one data output and sends said data output to at least one other of said multiport cell processors.

11. The node of claim 10 wherein said other multiport cell processor uses said data output to determine said other multiport cell processor'"'"'s state.

12. The node of claim 10 wherein said other multiport cell processor generates at least one said output overhead cell based on said data output.

13. The node of claim 8 wherein at least one of said multiport cell processors generates an error interrupt.

14. The node of claim 8 further comprising K buffers, wherein each of said K buffers is associated with a respective one of said K multiport cell processors, and wherein said dispatcher dispatches said input overhead blocks to each of said K multiport cell processors via said associated buffer.

15. An overhead processor in a node of a telecommunication network, said node having at least one input port and at least one output port, said overhead processor comprising:

a plurality of overhead engines, each of said overhead engines comprising

a dispatcher for

receiving input overhead cells, wherein each of said input overhead cells is associated with a respective one of said input ports, and

routing each of said input overhead cells to a non-empty subset of K multiport cell processors M₁ through M_K, wherein at least one of said multiport cell processors generates an output overhead cell based on at least one of said input overhead cells;

R aggregators A₁ through A_R, wherein each of said aggregators receives at least one of said output overhead cells and generates at least one output overhead block based on said output overhead cells, wherein said output overhead block is associated with one of a plurality of output ports; and

a scheduler for controlling said output ports'"'"' receiving of said overhead blocks from said aggregators; and

a load balancer for receiving said input overhead cells and routing each of said input overhead cells to a respective one of said overhead engines, wherein each of said input overhead cells is associated with a respective one of said input ports;

wherein K and R are positive integers.

16. The overhead processor of claim 15 wherein said load balancer routes said input overhead cells to said overhead engines based on a load balancing algorithm.

17. The overhead processor of claim 15 further comprising a master scheduler for further controlling said output ports'"'"' receiving of said overhead blocks from said overhead engines.

18. The overhead processor of claim 15 further comprising a switch and at least one input processor, said input processor for:

receiving input frames from a respective one of said input ports, wherein each of said input frames comprises a data portion and at least one of said input overhead cells;

transmitting said data portions to said switch; and

transmitting said input overhead cells to said overhead processor.

19. The overhead processor of claim 18 further comprising at least one output processor for:

receiving at least one of said data portions from said switch;

receiving at least one of said output overhead cells from said overhead engine;

building an output frame comprising at least one of said data portions and at least one of said output overhead cells; and

outputting said output frame on a respective one of said output ports.