Data processing system using internet protocols and RDMA
First Claim
1. A switching system having a plurality of line cards, each said line card having identification information based therein and comprising a hardware processor providing remote direct memory access capability for enabling data transfer using TCP over IP networks, said processor being programmable and sending and receiving data packets'"'"' also having identification information based therein, said packets transmitted, encapsulated or encoded using a iSCSI, iFCP, infiniband, SATA, SAS, IP, ICMP, IPSEC, DES, 3DES, AES, FC, SCSI, FCIP, NFS, CIFS, DAFS, HTTP, XML, XML derivative, SGML, or HTML format, or a combination of any of the foregoing.
4 Assignments
0 Petitions
Accused Products
Abstract
Disclosed are systems employing an architecture that provides capabilities to transport and process Internet Protocol (IP) packets from Layer 2 through transport protocol processing and may also perform packet inspection through Layer 7. A set of engines may perform passthrough packet classification, policy processing and/or security processing enabling packet streaming through the architecture at nearly the full line rate. A scheduler schedules packets to packet processors for processing. An internal memory or local session database cache stores a session information database for a certain number of active sessions. The session information that is not in the internal memory is stored and retrieved to/from an additional memory. An application running on an initiator or target can in certain instantiations register a region of memory, which is made available to its peer(s) for access directly without substantial host intervention through RDMA data transfer.
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Citations
110 Claims
- 1. A switching system having a plurality of line cards, each said line card having identification information based therein and comprising a hardware processor providing remote direct memory access capability for enabling data transfer using TCP over IP networks, said processor being programmable and sending and receiving data packets'"'"' also having identification information based therein, said packets transmitted, encapsulated or encoded using a iSCSI, iFCP, infiniband, SATA, SAS, IP, ICMP, IPSEC, DES, 3DES, AES, FC, SCSI, FCIP, NFS, CIFS, DAFS, HTTP, XML, XML derivative, SGML, or HTML format, or a combination of any of the foregoing.
- 7. A networking appliance comprising a hardware processor providing remote direct memory access capability for enabling data transfer from and to a data source, to and from a data destination, of data traffic transmitted, encapsulated or encoded using TCP over IP networks, said processor enabling said appliance to transport TCP/IP packets in-band to said data traffic or out of band to said data traffic.
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13. A host processor having a mother board, said motherboard having thereon one chip of a chip set, said one chip comprising a programmable hardware processor providing remote direct memory access capability for enabling data transfer using TCP, SCTP or UDP, or other session oriented protocol or a combination of any of the foregoing over IP networks.
- 14. A host having a mother board, said motherboard having thereon one chip of a chip set, said one chip containing a programmable hardware processor providing remote direct memory access capability for enabling data transfer using TCP, SCTP or UDP or a combination of any of the foregoing over IP networks, said processor having input and output queues and a RDMA controller, said queues and controller being maintained on said host.
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16. A multiprocessor system comprising at least one data processor coupled to a plurality of IP processors for interfacing said at least one data processor to said IP processors, each having RDMA capability for enabling TCP or SCTP or other session oriented protocols or UDP over IP:
- networks, said IP processor comprising;
a. a RDMA mechanism for performing RDMA data transfer;
b. at least one packet processor for processing IP packets;
c. a session memory for storing IP session information;
d. at least one memory controller for controlling memory accesses;
e. at least one media interface for coupling to at least one network; and
f. a host interface for coupling to at least one host or fabric interface for coupling to a fabric. - View Dependent Claims (17, 18, 19, 20, 21)
- networks, said IP processor comprising;
- 22. A peer system connected to a host system, each of said peer system and said host system comprising at least one hardware processor capable of executing a transport layer RDMA protocol on an IP Network.
- 34. A cluster of servers, a plurality of said servers having a hardware processor having RDMA capability for enabling data transfer over IP networks.
- 35. A cluster of servers, a plurality of said servers having a hardware processor having RDMA capability for enabling data transfer over Ethernet.
- 36. A central processing unit running a plurality of applications, said central processing unit having a separate hardware processor having RDMA capability for enabling data transfer over IP networks, said processor for communication among said applications running on said central processing unit.
- 45. A switching system comprising a plurality of line cards coupled to a switching fabric, said line cards including a processor capable of execution transport layer RDMA functions for processing Internet data packets in one or more sessions, said processor including a session memory for storing frequently or recently used session information for a plurality of sessions.
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51. The combination of a peer system connected to a host system, each of said peer system and said host system including at least one hardware processor capable of executing a transport layer RDMA protocol on an IP Network, said combination capable of performing (a) RDMA transfer from the peer system to the host system, (b) RDMA transfer from the host system to the peer system, and (c) RDMA transfer from the peer system to the host system and from the host system to the peer system concurrently.
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52. A server that is a blade server, thin server, appliance server, unix server, linux server, Windows or Windows derivative server, clustered server, database server, grid computing server, VoIP server, wireless gateway server, security server, file server, network attached server, media server, streaming media server or game server, or a combination of any of the foregoing, said server including a chipset containing a hardware processor providing a transport layer remote direct memory access capability over TCP, SCTP, UDP or other session oriented protocol on an IP network.
- 53. A server that is a blade server, thin server, appliance server, unix server, linux server, Windows or Windows derivative server, clustered server, database server, grid computing server, VoIP server, wireless gateway server, security server, file server, network attached server, media server, streaming media server or game server, or a combination of any of the foregoing, said server including a chipset containing a hardware processor providing remote direct memory access capability over a protocol other than TCP, SCTP or UDP.
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59. The server of claim 59, said processor included as a companion processor on said server chipset.
- 60. A storage controller for controlling storage and retrieval to and from a storage area network, of data transmitted over IP networks, said storage controller including a hardware processor providing a transport layer remote direct memory access capability for enabling storage using TCP, SCTP or UDP over IP.
- 80. A host processor for processing data packets received over the Internet, said host processor including a hardware processor providing a transport layer remote direct memory access capability for enabling storage using TCP, SCTP or UDP or other session oriented protocol over IP networks, said hardware processor providing offloading capability.
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86. An IP storage area network switching system line card having embedded therein a hardware processor providing remote direct memory access capability for enabling high-speed storage using TCP, SCTP or UDP over IP networks, said processor being programmable and operating on data packets transmitted, encapsulated or encoded using an iSCSI, iFCP, infiniband, SATA, SAS, IP, ICMP, IPSEC, DES, 3DES, AES, FC, SCSI, FCIP, NFS, CIFS, DAFS, HTTP, XML, XML derivative, SGML, or HTML format or a combination of any of the foregoing.
- 87. A gateway controller of a storage area network, said gateway controller including a chipset having embedded therein a hardware processor providing a transport layer remote direct memory access capability for enabling high-speed storage using TCP, SCTP or UDP over IP networks.
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89. A storage area network management appliance including a chipset having embedded therein a hardware processor providing a transport layer remote direct memory access capability for enabling transport of storage traffic using TCP, SCTP or UDP over IP networks, said hardware processor enabling said appliance to transport TCP/IP packets in-band to said traffic or out of band to said traffic.
- 90. A cluster of servers, each server including at least one chipset, at least one of said chipsets in said cluster having embedded therein a hardware processor providing remote direct memory access capability for enabling high-speed storage using TCP, SCTP or UDP over IP networks.
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92. A host processor running an application, said host processor including a hardware processor providing transport layer remote direct memory access (RDMA) capability, said hardware processor implemented for enabling high-speed storage using TCP, SCTP or UDP over IP networks, said hardware processor including:
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a. registration circuitry for allowing said application to register a memory region of said host processor with said hardware processor for RDMA access;
b. communication circuitry for allowing the exporting of said registered memory region to at least one peer hardware processor having RDMA capability and for allowing the informing of said peer of said host processor'"'"'s desire to allow said peer to read data from or write data to said registered memory region; and
c. RDMA circuitry for allowing information transfer to and from said registered region of memory without substantial host processor intervention.
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93. A host processor running an application, said host processor including a hardware processor providing transport layer remote direct memory access (RDMA) capability, said hardware processor implemented on an integrated circuit chip for enabling high-speed storage using TCP, SCTP or UDP over IP networks, the process of performing RDMA for said application including the steps of:
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a. said application registering a region of memory of said host processor for RDMA;
b. said hardware processor making said region of memory available to a peer processor having remote data transfer access capability without substantial intervention by said host processor in said data transfer;
c. said hardware processor communicating to said peer processor said host processor'"'"'s desire to allow said peer processor to read data from or write data to said region of memory; and
d. said hardware processor enabling information transfer from or to said registered region of memory without said host processor'"'"'s substantial intervention in said information transfer.
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94. A host processor having a SCSI command larger and an iSCSI driver, said host processor including a hardware processor including a transport layer RDMA capability for providing TCP/IP operations over a network for data packets from or to an initiator and providing said packets to or from said target, said operations requested by a host processor, said hardware processor comprising:
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a. an RDMA mechanism;
b. a command scheduler for scheduling commands from the command layer of said host processor for operation in said hardware processor;
c. first command queues for queuing commands from said host processor for existing sessions;
d. second command queues for queuing commands from said host processor for sessions that do not currently exist;
e. a database for recording the state of the session on which said command is transported, said database also for recording progress of RDMA for those of said commands that use RDMA;
f. a communication path between said hardware processor and said SCSI layer of said host processor for communicating status of command execution to said SCSI layer for processing; and
g. at least one transmit/receive engine and at least one command engine coupled together, said engines working together to interpret commands and perform appropriate operations for performing RDMA for retrieving data from or transmitting data to said host processor and for updating said state of said session. - View Dependent Claims (95, 96, 97, 98, 99, 100, 101, 102, 103)
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- 104. A storage array controller having a chipset for controlling a storage array, said controller including a hardware processor capable of providing remote direct memory access capability for enabling storage using TCP, SCTP or UDP or other session oriented protocol, or a combination of any of the foregoing, over IP networks, said processor controlling storage and retrieval, to and from said storage array, of data transmitted over IP networks, said processor included as a companion processor on said chipset.
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106. The packet processor of claim 106 further comprising (1) a packet processor engine, or (2) a TCP/IP processor engine, or (3) an IP Storage processor engine, or a combination of any of the foregoing.
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110. A network comprising one or more system, wherein said one or more system is a server, a host bus adapter, a switch, a switch line card, a gateway, a line card of a gateway, a storage area network appliance, a line card of an appliance, a storage system or a line card of a storage system or a combination of any of the foregoing, said one or more system comprising a hardware processor having transport layer RDMA capability for enabling data transfer using TCP or other session oriented protocols over IP networks, said processor being programmable and comprising a deep packet classification and/or policy processing engine, used by the said system to enable end to end network management for storage and/or non-storage data networks, said processor applying policies on a per packet, per flow, per command basis, or a combination of per packet, or per flow, or per command basis.
Specification