Data processing system using internet protocols and RDMA

• US 20040010545A1
• Filed: 06/10/2003
• Published: 01/15/2004
• Est. Priority Date: 06/11/2002
• Status: Active Grant

• Current Assignee: Memory Access Technologies LLC
• Original Assignee: Ashish A. Pandya
• Inventors: Pandya, Ashish A.
• Granted Patent: US 7,944,920 B2
• Time in Patent Office: Days
• US Class Current: 709/203
• CPC Class Codes: H04L 67/1097 for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
• CPC Class Codes: H04L 67/34 involving the movement of software or configuration parameters network booting or remote initial program loading [RIPL] G06F9/4416
• CPC Class Codes: H04L 69/10 Streamlined, light-weight or high-speed protocols, e.g. express transfer protocol [XTP] or byte stream
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
• CPC Class Codes: H04L 69/163 In-band adaptation of TCP data exchange; In-band control procedures
• CPC Class Codes: H04L 69/165 Combined use of TCP and UDP protocols; selection criteria therefor
• CPC Class Codes: H04L 69/166 IP fragmentation; TCP segmentation
• CPC Class Codes: H04L 69/18 Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
• CPC Class Codes: H04L 69/32 Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
• CPC Class Codes: H04L 69/323 in the physical layer [OSI layer 1]
• CPC Class Codes: H04L 69/326 in the transport layer [OSI layer 4] H04L69/16 takes precedence
• CPC Class Codes: H04L 69/329 in the application layer [OSI layer 7]
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

Disclosed are systems employing an architecture that provides capabilities to transport and process Internet Protocol (IP) packets from Layer 2 through transport protocol processing and may also perform packet inspection through Layer 7. A set of engines may perform passthrough packet classification, policy processing and/or security processing enabling packet streaming through the architecture at nearly the full line rate. A scheduler schedules packets to packet processors for processing. An internal memory or local session database cache stores a session information database for a certain number of active sessions. The session information that is not in the internal memory is stored and retrieved to/from an additional memory. An application running on an initiator or target can in certain instantiations register a region of memory, which is made available to its peer(s) for access directly without substantial host intervention through RDMA data transfer.

Claims

1. A switching system having a plurality of line cards, each said line card having identification information based therein and comprising a hardware processor providing remote direct memory access capability for enabling data transfer using TCP over IP networks, said processor being programmable and sending and receiving data packets'"'"' also having identification information based therein, said packets transmitted, encapsulated or encoded using a iSCSI, iFCP, infiniband, SATA, SAS, IP, ICMP, IPSEC, DES, 3DES, AES, FC, SCSI, FCIP, NFS, CIFS, DAFS, HTTP, XML, XML derivative, SGML, or HTML format, or a combination of any of the foregoing.

2. The switching system of claim 1 wherein the processor on a first of said plurality of line cards compares said destination information of said data packets with said identification information of a plurality of said plurality of line cards and transmits said packets to a second plurality of line cards based on said comparison.

3. The combination of claim 2 wherein said switching system provides multi-protocol support.

4. The combination of claim 2 wherein said switching system interfaces with an IP based storage area network and with a fibre channel, infiniband, serial ATA, SAS, IP Storage, or Ethernet protocol, or a combination of any of the foregoing, using a secure or a non-secure mode of data transfer.

5. The combination of claim 4 wherein said IP Storage protocol is iSCSI, FCIP, iFCP, or mFCP or a combination of any of the foregoing.

6. The combination of claim 4 terminating traffic in a first of said protocols and originating traffic in a second of said protocols.

109. The switching system of claim 1 wherein said processor operates on said packets to apply an access control, intrusion detection, bandwidth monitoring, bandwidth management, traffic shaping, security, virus detection, anti-spam, quality of service, encryption, decryption, LUN masking, zoning, multi-pathing, link aggregation or virtualization function or policy or a combination of any of the foregoing.

7. A networking appliance comprising a hardware processor providing remote direct memory access capability for enabling data transfer from and to a data source, to and from a data destination, of data traffic transmitted, encapsulated or encoded using TCP over IP networks, said processor enabling said appliance to transport TCP/IP packets in-band to said data traffic or out of band to said data traffic.

8. The appliance of claim 7 wherein said processor operates on said packets to apply an access control, intrusion detection, bandwidth monitoring, bandwidth management, traffic shaping, security, virus detection, anti-spam, quality of service, encryption, decryption, LUN masking, zoning, multi-pathing, link aggregation or virtualization function or policy or a combination of any of the foregoing.

9. The appliance of claim 7 wherein said processor is programmable and operates on data packets transmitted, encapsulated or encoded using an iSCSI, iFCP, infiniband, SATA, SAS, IP, ICMP, IPSEC, DES, 3DES, AES, FC, SCSI, FCIP, NFS, CIFS, DAFS, HTTP, XML, XML derivative, SGML, or HTML format or a combination of any of the foregoing.

10. The combination of claim 7 wherein said hardware processor itself includes a processor for performing deep packet inspection and classification.

11. The combination of claim 10 wherein said hardware processor itself includes a processor for performing policy management or policy enforcement on a packet-by-packet basis.

12. The combination of claim 11 wherein said hardware processor performs a function of virtualization, policy based management, policy enforcement, operations in-band to said data traffic or operations out of band to said data traffic.

28. The appliance of claim 7 wherein said processor operates on said packets to apply one or more policies on packets and said appliance is located in-band to said traffic to apply one or more policies on packets at substantially the full line rate.

29. The appliance of claim 7 wherein said processor operates on said packets to apply one or more policies on packets and said appliance is located out-of-band to said traffic.

30. The appliance of claim 28 wherein said appliance is coupled to the source and destination of said data transfer, said appliance collecting control and management information from said source and destination for use in controlling and managing said packets.

31. The appliance of claim 29 wherein said appliance is coupled to the source and destination of said data transfer, said appliance collecting control and management information from said source and destination for use in controlling and managing said packets.

32. The appliance of claim 28 wherein said one or more policies is access control, intrusion detection, bandwidth monitoring, bandwidth management, traffic shaping, security, virus detection, anti-spam, quality of service, encryption, decryption, LUN masking, multi-pathing, link aggregation, zoning, and virtualization

33. The appliance of claim 32 wherein said one or more policies is applied using deep packet inspection or packet header classification.

48. The combination of claim 8 wherein said processor itself includes a processor for performing deep packet inspection and classification.

49. The combination of claim 9 wherein said processor itself includes a processor for performing deep packet inspection and classification.

13. A host processor having a mother board, said motherboard having thereon one chip of a chip set, said one chip comprising a programmable hardware processor providing remote direct memory access capability for enabling data transfer using TCP, SCTP or UDP, or other session oriented protocol or a combination of any of the foregoing over IP networks.

14. A host having a mother board, said motherboard having thereon one chip of a chip set, said one chip containing a programmable hardware processor providing remote direct memory access capability for enabling data transfer using TCP, SCTP or UDP or a combination of any of the foregoing over IP networks, said processor having input and output queues and a RDMA controller, said queues and controller being maintained on said host.

15. The combination of claim 14, further comprising input and output queues and storage flow controller, said queues and said controller being implemented on a chip in said chipset other than a chip on a mother board of said host.

41. The host processor of claim 14 wherein said queues and said storage controller are maintained in software on said host processor.

42. The host processor of claim 14 including input and output queues and a storage flow controller, maintained partly in software on said host processor and partly in hardware on said programmable hardware processor.

43. The host processor of claim 14 including input and output queues and a storage flow controller, maintained partly in hardware on said host processor and partly in hardware on said programmable hardware processor.

44. The host processor of claim 14 including input and output queues and a storage flow controller, maintained partly in hardware and partly in software in said host processor, and partly in hardware on said programmable hardware processor.

50. The combination of claim 14, said queues and said controller being implemented on a chip in said chipset other than a chip on a mother board of said host.

16. A multiprocessor system comprising at least one data processor coupled to a plurality of IP processors for interfacing said at least one data processor to said IP processors, each having RDMA capability for enabling TCP or SCTP or other session oriented protocols or UDP over IP:

networks, said IP processor comprising;

a. a RDMA mechanism for performing RDMA data transfer;

b. at least one packet processor for processing IP packets;

c. a session memory for storing IP session information;

d. at least one memory controller for controlling memory accesses;

e. at least one media interface for coupling to at least one network; and

f. a host interface for coupling to at least one host or fabric interface for coupling to a fabric.

17. The multiprocessor system of claim 16, said IP network application processor further comprising at least one of:

a. an IP Storage session memory for storing IP Storage session information;

b. a classification processor for classifying IP packets;

c. a flow controller for controlling data flow;

d. a policy processor for applying policies;

e. a security processor for performing security operations;

f. a packet memory for storing packets;

g. a controller for control plane processing;

h. a packet scheduler;

i. a coprocessor interface for interfacing to a peer processor;

or

j. a combination of any of the foregoing.

18. The multiprocessor system of claim 16 wherein two or more of said plurality of IP processors are coupled to each other.

19. The multiprocessor system of claim 17 wherein two or more of said plurality of IP processors are coupled to each other.

20. The multiprocessor system of claim 18 wherein said two or more of said plurality of IP processors are coupled through a co-processor interface, or a host interface, or a bridge, or a combination of any of the foregoing.

21. The multiprocessor system of claim 19 wherein said two or more of said plurality of IP processors are coupled through a co-processor interface, or a host interface, or a bridge, or a combination of any of the foregoing.

22. A peer system connected to a host system, each of said peer system and said host system comprising at least one hardware processor capable of executing a transport layer RDMA protocol on an IP Network.

23. The combination of claim 22 performing RDMA transfer from the peer system to the host system.

24. The combination of claim 22 performing RDMA transfer from the host system to the peer system.

25. The combination of claim 23 further comprising an interface capable of being connected to a media access control layer of a host processor.

26. The combination of claim 24 further comprising an interface capable of being connected to a media access control layer of a host processor.

27. The combination of claim 22, performing RDMA transfer from the peer system to the host system and from the host system to the peer system concurrently.

34. A cluster of servers, a plurality of said servers having a hardware processor having RDMA capability for enabling data transfer over IP networks.

37. The combination of claim 34 wherein said data transfer is accomplished using a TCP, SCTP or UDP or other session oriented protocol or a combination of any of the foregoing.

39. The combination of claim 34 wherein said data transfer is accomplished using a protocol selected from the group of protocols consisting of the group or protocols excluding TCP, SCTP and UDP.

35. A cluster of servers, a plurality of said servers having a hardware processor having RDMA capability for enabling data transfer over Ethernet.

38. The combination of claim 35 wherein said data transfer is accomplished using a TCP, SCTP or UDP or other session oriented protocol or a combination of any of the foregoing.

40. The combination of claims 35 wherein said data transfer is accomplished using a protocol selected from the group of protocols consisting of the group or protocols excluding TCP, SCTP and UDP.

36. A central processing unit running a plurality of applications, said central processing unit having a separate hardware processor having RDMA capability for enabling data transfer over IP networks, said processor for communication among said applications running on said central processing unit.

107. The combination of claim 36 wherein said data transfer is accomplished using a TCP, SCTP or UDP or other session oriented protocol, or a combination of any of the foregoing.

108. The combination of claim 36 wherein said data transfer is accomplished using a protocol selected from the group of protocols other than TCP, SCTP or UDP.

45. A switching system comprising a plurality of line cards coupled to a switching fabric, said line cards including a processor capable of execution transport layer RDMA functions for processing Internet data packets in one or more sessions, said processor including a session memory for storing frequently or recently used session information for a plurality of sessions.

46. The switching system of claim 45 wherein said processor on at least one line card includes a host interface functioning as a fabric interface and said switching fabric is coupled to said fabric interface through a fabric controller.

47. The switching system of claim 45 wherein said fabric controller functions as an interface to said switching fabric, as a traffic manager as a traffic shaper or a combination of any of the foregoing.

51. The combination of a peer system connected to a host system, each of said peer system and said host system including at least one hardware processor capable of executing a transport layer RDMA protocol on an IP Network, said combination capable of performing (a) RDMA transfer from the peer system to the host system, (b) RDMA transfer from the host system to the peer system, and (c) RDMA transfer from the peer system to the host system and from the host system to the peer system concurrently.

52. A server that is a blade server, thin server, appliance server, unix server, linux server, Windows or Windows derivative server, clustered server, database server, grid computing server, VoIP server, wireless gateway server, security server, file server, network attached server, media server, streaming media server or game server, or a combination of any of the foregoing, said server including a chipset containing a hardware processor providing a transport layer remote direct memory access capability over TCP, SCTP, UDP or other session oriented protocol on an IP network.

53. A server that is a blade server, thin server, appliance server, unix server, linux server, Windows or Windows derivative server, clustered server, database server, grid computing server, VoIP server, wireless gateway server, security server, file server, network attached server, media server, streaming media server or game server, or a combination of any of the foregoing, said server including a chipset containing a hardware processor providing remote direct memory access capability over a protocol other than TCP, SCTP or UDP.

54. The server of claim 53 wherein said processor is programmable and operates on data packets transmitted, encapsulated or encoded using an iSCSI, iFCP, infiniband, SATA, SAS, IP, ICMP, IPSEC, DES, 3DES, AES, FC, SCSI, FCIP, NFS, CIFS, DAFS, HTTP, XML, XML derivative, SGML, or HTML format or a combination of any of the foregoing.

55. The server of claim 54 wherein said processor is programmable and operates on data packets transmitted, encapsulated or encoded using an iSCSI, iFCP, infiniband, SATA, SAS, IP, ICMP, IPSEC, DES, 3DES, AES, FC, SCSI, FCIP, NFS, CIFS, DAFS, HTTP, XML, XML derivative, SGML, or HTML format or a combination of any of the foregoing.

56. The server of claim 55 wherein said processor has certain of its functions implemented in hardware and certain of its functions implemented in software.

57. The server of claim 56 wherein said processor has certain of its functions implemented in hardware and certain of its functions implemented in software.

58. The server of claim 57, said processor included as a companion processor on said server chipset.

72. The combination of claim 53 wherein said server includes a host adapter card and said processor is embedded in said host adapter card for providing high-speed TCP, SCTP, UDP, or other session oriented protocol networking capability.

73. The combination of claim 54 wherein said server includes a host adapter card and said processor is embedded in said host adapter card for providing high-speed networking capability.

74. The combination of claim 72 wherein said host adapter card is capable of accessing network storage to transmit data to said storage over the Internet.

75. The combination of claim 73 wherein said host adapter card is capable of accessing network storage to transmit data to said storage over the Internet.

76. The combination of claim 72 wherein said adapter card is used as a blade in a scalable blade server.

77. The combination of claim 73 wherein said host adapter card is used as a blade in a scalable blade server.

78. The combination of claim 72 wherein said host adapter card is in the front end of a storage array front end.

79. The combination of claim 73 wherein said host adapter card is in the front end of a storage array front end.

59. The server of claim 59, said processor included as a companion processor on said server chipset.

60. A storage controller for controlling storage and retrieval to and from a storage area network, of data transmitted over IP networks, said storage controller including a hardware processor providing a transport layer remote direct memory access capability for enabling storage using TCP, SCTP or UDP over IP.

61. The storage controller of claim 60 wherein said hardware processor is included as a companion processor on a chipset of said storage controller.

62. The storage controller of claim 60 wherein said processor is programmable and operates on data packets transmitted, encapsulated or encoded using an iSCSI, iFCP, infiniband, SATA, SAS, IP, ICMP, IPSEC, DES, 3DES, AES, FC, SCSI, FCIP, NFS, CIFS, DAFS, HTTP, XML, XML derivative, SGML, or HTML format or a combination of any of the foregoing.

63. The storage controller of claim 61 wherein said processor is programmable and operates on data packets transmitted, encapsulated or encoded using an iSCSI, iFCP, infiniband, SATA, SAS, IP, ICMP, IPSEC, DES, 3DES, AES, FC, SCSI, FCIP, NFS, CIFS, DAFS, HTTP, XML, XML derivative, SGML, or HTML format or a combination of any of the foregoing.

64. The combination of claim 60 wherein said processor (1) is embedded on a chipset on the storage controller'"'"'s motherboard, or (2) includes the function of data packet security, or (3) includes the function of data packet scheduling, or (3) includes the function of data packet classification.

65. The combination of claim 61 wherein said processor (1) is embedded on a chipset on the storage controller'"'"'s motherboard, or (2) includes the function of data packet security, or (3) includes the function of data packet scheduling, or (3) includes the function of data packet classification.

66. The combination of claim 60 wherein said processor provides IP network storage capability for said storage controller to operate in an IP based storage area network.

67. The combination of claim 61 wherein said processor provides IP network storage capability for said storage controller to operate in an IP-based storage area network.

68. The combination of claim 60 wherein said storage controller includes a blade controller having an interface to said storage area network.

69. The combination of claim 63 wherein said storage controller includes a blade controller having an interface to said storage area network and said chipset is in said interface.

70. The combination of claim 60 further comprising at least one storage array, said storage controller providing access said at least one storage array and controlling the storage function in said at least one storage array.

71. The combination of claim 61 further comprising at least one storage array, said storage controller providing access said at least one storage array and controlling the storage function in said at least one storage array.

80. A host processor for processing data packets received over the Internet, said host processor including a hardware processor providing a transport layer remote direct memory access capability for enabling storage using TCP, SCTP or UDP or other session oriented protocol over IP networks, said hardware processor providing offloading capability.

81. The combination of claim 80 wherein said hardware processor is programmable and operates on data packets transmitted, encapsulated or encoded using an iSCSI, iFCP, infiniband, SATA, SAS, IP, ICMP, IPSEC, DES, 3DES, AES, FC, SCSI, FCIP, NFS, CIFS, DAFS, HTTP, XML, XML derivative, SGML, or HTML format or a combination of any of the foregoing.

82. The combination of claim 80 wherein said host processor is a high end server, workstation, personal computers capable of interfacing with high speed networks, wireless LAN, hand held wireless telecommunication device, router, switch, gateway, blade server, thin server, media server, streaming media server, appliance server, Unix server, Linux server, Windows or Windows derivative server, AIX server, clustered server, database server, grid computing server, VoIP server, wireless gateway server, security server, file server, network attached storage server, game server or a combination of any of the foregoing.

83. The combination of claim 81 wherein said host processor is a high end server, workstation, personal computers capable of interfacing with high speed networks, wireless LAN, hand held wireless telecommunication device, router, switch and gateway, blade server, thin server, media server, streaming media server, appliance server, Unix server, Linux server, Windows or Windows derivative server, AIX server, clustered server, database server, grid computing server, VoIP server, wireless gateway server, security server, file server, network attached storage server, game server or a combination of any of the foregoing.

84. The combination of claim 82 wherein at least one member of said group of recited apparati is a low power apparatus.

85. The combination of claim 83 wherein at least one member of said group of recited apparati is a low power apparatus.

86. An IP storage area network switching system line card having embedded therein a hardware processor providing remote direct memory access capability for enabling high-speed storage using TCP, SCTP or UDP over IP networks, said processor being programmable and operating on data packets transmitted, encapsulated or encoded using an iSCSI, iFCP, infiniband, SATA, SAS, IP, ICMP, IPSEC, DES, 3DES, AES, FC, SCSI, FCIP, NFS, CIFS, DAFS, HTTP, XML, XML derivative, SGML, or HTML format or a combination of any of the foregoing.

87. A gateway controller of a storage area network, said gateway controller including a chipset having embedded therein a hardware processor providing a transport layer remote direct memory access capability for enabling high-speed storage using TCP, SCTP or UDP over IP networks.

88. The combination of claim 87 wherein said hardware processor is programmable and operates on data packets transmitted, encapsulated or encoded using an iSCSI, iFCP, infiniband, SATA, SAS, IP, ICMP, IPSEC, DES, 3DES, AES, FC, SCSI, FCIP, NFS, CIFS, DAFS, HTTP, XML, XML derivatives, SGML, or HTML format or a combination of any of the foregoing.

89. A storage area network management appliance including a chipset having embedded therein a hardware processor providing a transport layer remote direct memory access capability for enabling transport of storage traffic using TCP, SCTP or UDP over IP networks, said hardware processor enabling said appliance to transport TCP/IP packets in-band to said traffic or out of band to said traffic.

90. A cluster of servers, each server including at least one chipset, at least one of said chipsets in said cluster having embedded therein a hardware processor providing remote direct memory access capability for enabling high-speed storage using TCP, SCTP or UDP over IP networks.

91. The combination of claim 90 wherein said hardware processor is programmable and operates on data packets transmitted, encapsulated or encoded using an iSCSI, iFCP, infiniband, SATA, SAS, IP, ICMP, IPSEC, DES, 3DES, AES, FC, SCSI, FCIP, NFS, CIFS, DAFS, HTTP, XML, XML derivatives, SGML, or HTML format or a combination of any of the foregoing.

92. A host processor running an application, said host processor including a hardware processor providing transport layer remote direct memory access (RDMA) capability, said hardware processor implemented for enabling high-speed storage using TCP, SCTP or UDP over IP networks, said hardware processor including:

a. registration circuitry for allowing said application to register a memory region of said host processor with said hardware processor for RDMA access;

b. communication circuitry for allowing the exporting of said registered memory region to at least one peer hardware processor having RDMA capability and for allowing the informing of said peer of said host processor'"'"'s desire to allow said peer to read data from or write data to said registered memory region; and

c. RDMA circuitry for allowing information transfer to and from said registered region of memory without substantial host processor intervention.

93. A host processor running an application, said host processor including a hardware processor providing transport layer remote direct memory access (RDMA) capability, said hardware processor implemented on an integrated circuit chip for enabling high-speed storage using TCP, SCTP or UDP over IP networks, the process of performing RDMA for said application including the steps of:

a. said application registering a region of memory of said host processor for RDMA;

b. said hardware processor making said region of memory available to a peer processor having remote data transfer access capability without substantial intervention by said host processor in said data transfer;

c. said hardware processor communicating to said peer processor said host processor'"'"'s desire to allow said peer processor to read data from or write data to said region of memory; and

d. said hardware processor enabling information transfer from or to said registered region of memory without said host processor'"'"'s substantial intervention in said information transfer.

94. A host processor having a SCSI command larger and an iSCSI driver, said host processor including a hardware processor including a transport layer RDMA capability for providing TCP/IP operations over a network for data packets from or to an initiator and providing said packets to or from said target, said operations requested by a host processor, said hardware processor comprising:

a. an RDMA mechanism;

b. a command scheduler for scheduling commands from the command layer of said host processor for operation in said hardware processor;

c. first command queues for queuing commands from said host processor for existing sessions;

d. second command queues for queuing commands from said host processor for sessions that do not currently exist;

e. a database for recording the state of the session on which said command is transported, said database also for recording progress of RDMA for those of said commands that use RDMA;

f. a communication path between said hardware processor and said SCSI layer of said host processor for communicating status of command execution to said SCSI layer for processing; and

g. at least one transmit/receive engine and at least one command engine coupled together, said engines working together to interpret commands and perform appropriate operations for performing RDMA for retrieving data from or transmitting data to said host processor and for updating said state of said session.

95. The combination of claim 94 wherein said at least one transmit/receive engine is implemented as a separate transmit engine and a separate receive engine.

96. The combination of claim 94 wherein said first command queues are located partly in memory on said hardware processor and partly in memory off said hardware processor.

97. The combination of claim 94 wherein said second command queues are located partly in memory on said hardware processor and partly in memory off said hardware processor.

98. The combination of claim 94 wherein said memory off said hardware processor is memory in said host processor and memory on a chip not included in said host processor.

99. The combination of claim 95 wherein said memory off said hardware processor is memory in said host processor and memory on a chip not included in said host processor.

100. The combination of claim 98 wherein said memory on a chip not included in said host processor is RAM, DRAM, SDRAM, DDR SDRAM, RDRAM, FCRAM, FLASH, ROM, EPROM, EEPROM, QDR SRAM QDR DRAM and other derivatives of static or dynamic random access memory, or a combination of any of the foregoing.

101. The combination of claim 98 wherein said memory on a chip not included in said host processor is located on a companion chip to said hardware processor.

102. The combination of claim 99 wherein said memory on a chip not included in said host processor is RAM, DRAM, SDRAM, DDR SDRAM, RDRAM, FCRAM, FLASH, ROM, EPROM, EEPROM, QDR SRAM QDR DRAM and other derivatives of static or dynamic random access memory, or a combination of any of the foregoing.

103. The combination of claim 99 wherein said memory on a chip not included in said host processor is located on a companion chip to said hardware processor.

104. A storage array controller having a chipset for controlling a storage array, said controller including a hardware processor capable of providing remote direct memory access capability for enabling storage using TCP, SCTP or UDP or other session oriented protocol, or a combination of any of the foregoing, over IP networks, said processor controlling storage and retrieval, to and from said storage array, of data transmitted over IP networks, said processor included as a companion processor on said chipset.

105. The combination of claim 104 wherein said processor provides IP network storage capability for said storage array controller to operate in an IP based storage area network.

106. The packet processor of claim 106 further comprising (1) a packet processor engine, or (2) a TCP/IP processor engine, or (3) an IP Storage processor engine, or a combination of any of the foregoing.

110. A network comprising one or more system, wherein said one or more system is a server, a host bus adapter, a switch, a switch line card, a gateway, a line card of a gateway, a storage area network appliance, a line card of an appliance, a storage system or a line card of a storage system or a combination of any of the foregoing, said one or more system comprising a hardware processor having transport layer RDMA capability for enabling data transfer using TCP or other session oriented protocols over IP networks, said processor being programmable and comprising a deep packet classification and/or policy processing engine, used by the said system to enable end to end network management for storage and/or non-storage data networks, said processor applying policies on a per packet, per flow, per command basis, or a combination of per packet, or per flow, or per command basis.