SDRAM structure and method of fabricating the same

• US 20040012045A1
• Filed: 02/13/2003
• Published: 01/22/2004
• Est. Priority Date: 07/22/2002
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Lee, Chin
• Granted Patent: US 6,774,424 B2
• Time in Patent Office: Days
• US Class Current: 257/306
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/373 the capacitor extending under or around the transistor

Abstract

A synchronous dynamic random access memory (SDRAM) structure is provided. A stacked capacitor structure and a trench capacitor structure are integrated together within each memory cell such that the two capacitors overlap over each other to reduce overall area occupation of the SDRAM array.

Claims

1. A synchronous dynamic random access memory (SDRAM) structure, comprising:

a substrate;

a plurality of first transistors over the substrate, wherein each first transistor has a first gate and a pair of first source/drain terminals;

a plurality of trench capacitor structures within the substrate, wherein the trench capacitor structures connect electrically with the respective first source/drain terminals;

an epitaxial layer over the substrate;

a plurality of second transistors over the epitaxial layer, wherein each second transistor has a second gate and a pair of second source/drain terminals;

a plurality of stacked capacitor structure over the epitaxial layer above the trench capacitor structure, wherein the stacked capacitor structures connect electrically with the respective second source/drain terminals; and

a plurality of bit lines above the first transistors and the second transistors, wherein the bit lines connect electrically with the first source/drain terminals and the second source/drain terminals respectively.

2. The SDRAM structure of claim 1, wherein the substrate is a silicon substrate.

3. The SDRAM structure of claim 1, wherein the epitaxial layer is a silicon epitaxial layer.

4. The SDRAM structure of claim 1, wherein each first transistor comprises a first gate insulation layer between the substrate and the first gate.

5. The SDRAM structure of claim 1, wherein each first transistor comprises a second gate insulation layer between the substrate and the second gate.

6. The SDRAM structure of claim 1, wherein each trench capacitor structurecomprises:

an electrode electrically connected with the first source/drain terminal;

an N-doped region in the substrate around the electrode; and

a first capacitor dielectric layer between the electrode and the N-doped region.

7. The SDRAM structure of claim 6, wherein the electrode comprises an N-doped polysilicon layer.

8. The SDRAM structure of claim 6, wherein the first capacitor dielectric layer comprises a silicon nitride layer.

9. The SDRAM structure of claim 6, wherein each stacked capacitor structurecomprises:

a lower electrode electrically connected with the second source/drain terminal;

an upper electrode above the lower electrode; and

a second capacitor dielectric layer between the upper electrode and the lower electrode.

10. The SDRAM structure of claim 9, wherein the lower electrode comprises a polysilicon layer.

11. The SDRAM structure of claim 9, wherein the upper electrode comprises a polysilicon layer.

12. The SDRAM structure of claim 9, wherein the second capacitor dielectric layer comprises a silicon nitride layer.

13. A layout structure for a synchronous dynamic random access memory, comprising:

a first sense amplifier;

a plurality of first memory cells on one side of the first sense amplifier;

a first bit line serially connecting the first memory cells and the first sense amplifier;

a plurality of second memory cells on a second side of the first sense amplifier;

a second bit line serially connecting the second memory cells and the first sense amplifier;

a second sense amplifier;

a plurality of third memory cells on one side of the second sense amplifier that corresponds in position to the first memory cells; and

a word line connected to at least a first memory cell and at least a third memory cell.