Semiconductor leadframes having dual surface finish for varied molding compound adhesion

• US 20040012077A1
• Filed: 07/22/2002
• Published: 01/22/2004
• Est. Priority Date: 07/22/2002
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Ibrahim, Mohd A., Huckabee, James R.
• Application Number:
  US10/200,277
• Publication Number:
  US 20040012077A1
• Time in Patent Office: Days
• US Class Current: 257/666
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48 of an individual wire connector
• CPC Class Codes: H01L 23/49565 Side rails of the lead frame, e.g. with perforations, sprocket holes
• CPC Class Codes: H01L 23/49582 Metallic layers on lead frames
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01028 Nickel [Ni]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

A leadframe strip for use in the assembly of integrated circuit devices, which is made from a sheet of base metal and comprises a series of leadframe units formed in this base metal. The units are arranged in linear progression so that each unit is interconnected with its adjacent neighbors by supporting rails. The rails are positioned along the outer edges of the strip, thus holding the strip together. The strip has a surface configuration for the leadframe units such that the surface maximizes adhesion to the encapsulation material. The strip further has a surface configuration for the rails such that the surface minimizes adhesion to the encapsulation material.

Claims

1. A leadframe strip for use in the assembly and packaging of integrated circuit devices, said strip made from a sheet of base metal and said packaging including encapsulation material, comprising:

a series of leadframe units formed in said base metal and arranged in linear progression so that each unit is interconnected with its adjacent neighbors by supporting rails, wherein said rails are positioned along the outer edges of said strip, thus holding said strip together;

a surface configuration of said base metal for said leadframe units such that said surface maximizes adhesion to said encapsulation material; and

a surface configuration of said base metal for said rails such that said surface minimizes adhesion to said encapsulation material.

2. The leadframe strip according to claim 1 wherein said base metal is copper, copper alloy, aluminum, iron-nickel alloy, or invar.

3. The leadframe strip according to claim 1 wherein said sheet metal has a thickness between 100 and 300 μ

m.

4. The leadframe strip according to claim 1 wherein said surface configuration of said base metal for said leadframe units comprises an adherent layer of nickel on said base metal, and a layer of palladium or palladium/gold adherent on said nickel.

5. The leadframe strip according to claim 4 wherein said nickel layer has a thickness between 0.2 and 3.0 μ

m.

6. The leadframe strip according to claim 4 wherein said palladium layer has a thickness between 20 and 75 nm.

7. The leadframe strip according to claim 4 wherein said gold layer has a thickness between 2 and 5 nm.

8. The leadframe strip according to claim 1 wherein said surface configuration of said base metal for said rails comprises said base metal as modified by the manufacturing process flow.

9. The leadframe strip according to claim 1 wherein said surface configuration of said base metal for said rails comprises an adherent layer of nickel on said base metal.

10. The leadframe strip according to claim 9 wherein said nickel layer has a thickness between 0.2 and 3.0 μ

m.

11. A leadframe strip for use in the assembly of integrated circuit devices, said strip made from a sheet of base metal, comprising:

a series of leadframe units formed in said base metal and arranged in linear progression so that each unit is interconnected with its adjacent neighbors by supporting rails, wherein said rails are positioned along the outer edges of said strip, thus holding said strip together;

said strip having an adherent first layer comprising nickel on said base metal; and

an adherent second layer of metal on said nickel layer, wherein said second metal is selected for improved adherence to encapsulation compounds and bonding wires;

said second layer selectively placed on said units, leaving said rails uncovered.

12. A method for fabricating a leadframe strip for use in the assembly and packaging of integrated circuit devices, comprising the steps of:

forming a plurality of leadframe units from a sheet of base metal, each of said units comprising a mount pad for an integrated circuit chip and a plurality of lead segments, said series of units arranged in linear progression so that each unit is interconnected with its adjacent neighbors by supporting rails, wherein said rails are positioned along the outer edges of said strip and are holding said strip together;

selectively masking said rails, thereby leaving said leadframe units exposed;

plating a layer of a metal selected for improved adherence to encapsulation compounds and bonding wires; and

removing said selective mask from said rails.

13. The method according to claim 12 wherein said step of forming a plurality of leadframe units comprises the step of stamping.

14. The method according to claim 12 wherein said step of forming a plurality of leadframe units comprises the step of etching.

15. The method according to claim 12 further comprising the step of plating an additional layer of metal on said leadframe before said layer for improved adhesion is plated.

16. A method for fabricating a semiconductor device using

a transfer molding encapsulation process, comprising:

providing a plurality of integrated circuit chips;

providing a leadframe strip having a series of leadframe units arranged in linear progression so that each unit is interconnected with its adjacent neighbors by supporting rails, wherein said rails are positioned along the outer edges of said strip, thus holding said strip together;

said strip having a metal-containing layer selected for improved adherence to encapsulation compounds and bonding wires, selectively placed on said units so that said rails remain uncovered;

attaching one of said chips at a time to its respective leadframe unit;

wire bonding each of said chips to their respective electrical leadframe connections, completing the assembly of said chips;

placing said strip into the cavity of a mold, closing said mold and pressuring molding compound through runners and a gate into said cavity for encapsulating said assembled chips, whereby said compound in said runners, in order to reach said gates into said cavity, crosses said rails without adhering to said rails;

opening said mold for unloading said strip, thereby separating said rails from said compound remaining in said runners.

17. The method according to claim 16 wherein said metal-containing layer is selected in conjunction with said molding compound so that said their mutual adhesion is maximized.

18. The method according to claim 16 wherein said metal layer for improved adherence comprises palladium or palladium/gold.

19. The method according to claim 16 wherein said layer for improved adherence comprises a metal oxide.