Connection of integrated circuits

• US 20040012080A1
• Filed: 05/28/2003
• Published: 01/22/2004
• Est. Priority Date: 05/28/2002
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Hedler, Harry, Pohl, Jens, Irsigler, Roland
• Granted Patent: US 6,979,591 B2
• Time in Patent Office: Days
• US Class Current: 257/678
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48471 the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01059 : Praseodymium [Pr]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

The present invention provides a method of connecting integrated circuits and a corresponding assembly of integrated circuits. Connecting occurs by performing the steps of: providing a first integrated circuit (C1), which has a first wiring device (K, BP, 4, 41-48, 161-168) on a first main area (HF2), and a second integrated circuit (C2), which has a second wiring device (K, BP, 4, 61-68, 261-268) on a second main area (HF2); at least one of the first wiring device (K, BP, 4, 41-48, 161-168) and second wiring device (K, BP, 4, 61-68, 261-268) having a number of elevated contact areas (161-168, 261-268), which lie on respective elastic elevations (31-38, 51-58), and the other of the first wiring device (K, BP, 4, 41-48, 161-168) and second wiring device (K, BP, 4, 61-68, 261-268) having a number of non-elevated contact areas (61-68, 41-47), which can be aligned in relation to the elevated contact areas (161-168, 261-268); applying a liquid adhesive (300) to at least one of the first and second main areas (HF1, HF2); aligning the first and second main areas (HF1, HF2), so that the non-elevated contact areas (61-68, 41-47) electrically contact the corresponding elevated contact areas (161-168, 261-268); and curing the adhesive (300).

Claims

1. Method of connecting integrated circuits, in particular of chips, with the steps of:

providing a first integrated circuit (C1), which has a first wiring device (K, BP, 4, 41-48, 161-168) on a first main area (HF2), and a second integrated circuit (C2), which has a second wiring device (K, BP, 4, 61-68, 261-268) on a second main area (HF2);

at least one of the first wiring device (K, BP, 4, 41-48, 161-168) and second wiring device (K, BP, 4, 61-68, 261-268) having a number of elevated contact areas (161-168, 261-268), which lie on respective elastic elevations (31-38, 51-58), and the other of the first wiring device (K, BP, 4, 41-48, 161-168) and second wiring device (K, BP, 4, 61-68, 261-268) having a number of non-elevated contact areas (61-68, 41-47), which can be aligned in relation to the elevated contact areas (161-168, 261-268);

applying a liquid adhesive (300) to at least one of the first and second main areas (HF1, HF2);

aligning the first and second main areas (HF1, HF2), so that the non-elevated contact areas (61-68, 41-47) electrically contact the corresponding elevated contact areas (161-168, 261-268); and

curing the adhesive (300) for firmly connecting the integrated circuits (C1, C2).

2. Method according to claim 1, characterized in that pressing together of the first and second main areas (HF1, HF2) is carried out, so that the elevated contact areas (161-168, 261-268) are deformed.

3. Method according to claim 2, characterized in that the curing of the adhesive (300) takes place at least partly while the elevated contact areas (161-168, 261-268) are deformed, so that the deformations are frozen in.

4. Method according to one of the preceding claims, characterized in that the first integrated circuit (C1) is mounted on a substrate (P) before the alignment.

5. Method according to claim 4, characterized in that, before the alignment, contact areas (BP′

) on the substrate (P) are connected to contact areas (BP) on the first main area (HF1) by bonding wires (9).

6. Method according to one of the preceding claims, characterized in that a multiplicity of pairs of a first and second circuit device (C1, C2) are simultaneously aligned and firmly connected.

7. Method according to one of the preceding claims, characterized in that the integrated circuits (C1, C2) are provided in wafer form, chip form or hybrid form.

8. Method according to one of the preceding claims, characterized in that the elevated contact areas are connected together with the non-elevated contact areas by means of solder or an electrically conducting adhesive.

14. Assembly according to one of the preceding claims, characterized in that the elevated contact areas are connected together with the non-elevated contact areas by means of solder or an electrically conducting adhesive.

9. Assembly of integrated circuits, in particular of chips, with:

a first integrated circuit (C1), which has a first wiring device (K, BP, 4, 41-48, 161-168) on a first main area (HF2), and a second integrated circuit (C2), which has a second wiring device (K, BP, 4, 61-68, 261-268) on a second main area (HF2);

at least one of the first wiring device (K, BP, 4, 41-48, 161-168) and second wiring device (K, BP, 4, 61-68, 261-268) having a number of elevated contact areas (161-168, 261-268), which lie on respective elastic elevations (31-38, 51-58), and the other of the first wiring device (K, BP, 4, 41-48, 161-168) and second wiring device (K, BP, 4, 61-68, 261-268) having a number of non-elevated contact areas (61-68, 41-47), which are directed toward the elevated contact areas (161-168, 261-268) and are pressed against them in such a way that the non-elevated contact areas (61-68, 41-47) electrically contact the corresponding elevated contact areas (161-168, 261-268);

a cured adhesive (300) for connecting the first and second main areas (HF1, HF2).

10. Assembly according to claim 9, characterized in that the elevated contact areas (161-168, 261-268) are deformed.

11. Assembly according to claims 9 or 10, characterized in that the first integrated circuit (C1) is mounted on a substrate (P).

12. Assembly according to claim 11, characterized in that contact areas (BP′

) on the substrate (P) are bonded to contact areas (BP) on the first main area (HF1).

13. Assembly according to one of the preceding claims 9 to 12, characterized in that the integrated circuits (C1, C2) are provided in wafer form, chip form or hybrid form.