Method and packaging structure for optimizing warpage of flip chip organic packages

• US 20040012086A1
• Filed: 07/17/2002
• Published: 01/22/2004
• Est. Priority Date: 07/17/2002
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Sathe, Sanjeev Balwant, Li, Li, Rosser, Steven G., Infantolino, William
• Granted Patent: US 6,747,331 B2
• Time in Patent Office: Days
• US Class Current: 257/730
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3511 Warping

Abstract

An electronic packaging structure and method of forming thereof wherein the structure is constituted of a modular arrangement which reduces stresses generated in a chip, underfill, and ball grid array connection with a flexible substrate in the form of an organic material, which stresses may result in potential delamination due to thermally-induced warpage between the components of the modular arrangement.

Claims

1. An electronic package comprising at least one semiconductor chip mounted on an organic substrate, said at least one semiconductor chip having edge portions forming at least one corner point;

said organic substrate having edge portions forming at least two corner points at distal edge portions thereof, whereby said at least one corner point of said at least one semiconductor chip is angularly rotated about a z-axis through a neutral point relative to said at least two corner points of said substrate substantially subtending a predetermined angular displacement between the corner points of said substrate and the at least one corner point of said at least one semiconductor chip so as to reduce warpage between said at least one semiconductor chip and said organic substrate caused by thermally-induced stresses generated therebetween at said corner points.

2. An electronic package as claimed in claim 1, wherein at least one solder joint array corner point is provided between said at least corner point of said at least one semiconductor chip and said organic substrate, said at least one solder joint array corner point being in superimposed alignment with said at least one corner point of said at least one semiconductor chip.

3. An electronic package as claimed in claim 1, wherein said at least one corner point on said at least one semiconductor chip is rotated in the z-axis through said neutral point from at least one corner point on said organic substrate by an angular displacement of about 45°

.

4. An electronic package as claimed in claim 1, wherein a thermally curable adhesive underfill material is provided between said at least one semiconductor chip and said organic substrate, whereby cooling of said underfill material or thermal cycling of said electronic package generates stresses causing warpage between the components of said package.

5. An electronic package as claimed in claim 1, wherein said at least one semiconductor chip comprises silicon having a coefficient of thermal expansion of about 3 ppm./°

C.

6. An electronic package as claimed in claim 1, wherein said organic substrate comprises an epoxy having a coefficient of thermal expansion of about 18 ppm/°

C.

7. An electronic package as claimed in claim 3, wherein said neutral point coincides with a center point of said at least one semiconductor chip, and a maximum bending shear deformation of said electronic package occurs at least at one corner point of said organic substrate distant from said neutral point (DNP).

8. A method of forming an electronic package, comprising:

providing at least one semiconductor chip having edge portions forming at least one corner point;

providing an organic substrate having edge portions forming at least two corner points at distal edge portions thereof;

and mounting said at least one semiconductor chip in surface-to-surface engagement on said organic substrate such that said at least one corner point of said at least one semiconductor chip is rotated about a z-axis through a neutral point relative to said at least two corner points of said substrate subtending a predetermined angular displacement between the corner points of said organic substrate and the at least one corner point of said at least one semiconductor chip so as to reduce warpage between said at least one semiconductor chip and said organic substrate caused by thermally-induced stresses generated therebetween at said corner points.

9. A method as claimed in claim 8, wherein at least one solder joint array corner point is provided between said at least corner point of said at least one semiconductor chip and said organic substrate, said at least one solder joint array corner point being in superimposed alignment with said at least one corner point of said at least one semiconductor chip.

10. A method as claimed in claim 8, wherein said at least one corner point on said at least one semiconductor chip is rotated about in the z-axis through said neutral point from at least one corner point on said organic substrate by an angular displacement of about 45°

.

11. A method as claimed in claim 8, wherein a thermally curable adhesive underfill material is provided between said at least one semiconductor chip and said organic substrate, whereby cooling of said underfill material or thermal cycling of said electronic package generates stresses causing warpage between the components of said package.

12. A method as claimed in claim 8, wherein said at least one semiconductor chip comprises silicon having a coefficient of thermal expansion of about 3 ppm./°

C.

13. A method as claimed in claim 8, wherein said organic substrate comprises an epoxy having a coefficient of thermal expansion of about 18 ppm/°

C.

14. A method as claimed in claim 10, wherein said neutral point coincides with a center point of said at least one semiconductor chip, and a maximum bending shear deformation of said electronic package occurs at least at one corner point of said organic substrate distant from said neutral point (DNP).

15. An electronic package comprising at least one rectangular semiconductor chip mounted on an organic substrate, said at least one semiconductor chip having edge portions forming corner points;

said organic substrate having edge portions forming at least two corner points at distal edge portions thereof, the corner points of said at least one semiconductor chip being angularly rotated about a z-axis extending through a neutral point located at the center of said at least one rectangular semiconductor chip relative to said at least two corner points of said substrate substantially subtending a predetermined angular displacement between the corner points of said substrate and the corner points of said at least one semiconductor chip so as to reduce warpage between said at least one semiconductor chip and said organic substrate caused by thermally-induced stresses generated therebetween at said corner points.

16. An electronic package as claimed in claim 15, wherein solder joint array corner points are provided between said corner points of said at least one semiconductor chip and said organic substrate, said solder joint array corner points being in superimposed alignment with said corner point of said at least one semiconductor chip.

17. An electronic package as claimed in claim 15, wherein said corner points on said at least one semiconductor chip are rotated about the z-axis about a neutral point from the corner points said organic substrate by an angular displacement of about 45°

.

18. An electronic package as claimed in claim 15, wherein a thermally curable adhesive underfill material is provided between said at least one semiconductor chip and said organic substrate, whereby cooling of said underfill material or thermal cycling of said electronic package generates stresses causing warpage between the components of said package.

19. An electronic package as claimed in claim 15, wherein said at least one semiconductor chip comprises silicon having a coefficient of thermal expansion of about 3 ppm./°

C.

20. An electronic package as claimed in claim 15, wherein said organic substrate comprises an epoxy having a coefficient of thermal expansion of about 18 ppm/°

C.