Systems and methods of bidirectional communication across an isolation barrier

• US 20040012515A1
• Filed: 12/07/2002
• Published: 01/22/2004
• Est. Priority Date: 12/10/2001
• Status: Active Grant

• Current Assignee: Maxlinear Incorporated
• Original Assignee: Infineon Technologies North America Corporation (Infineon Technologies AG)
• Inventors: Osborne, Thomas W.
• Granted Patent: US 6,965,336 B2
• Time in Patent Office: Days
• US Class Current: 341/155
• CPC Class Codes: H04L 25/0266 Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling
• CPC Class Codes: H04L 25/062 Setting decision thresholds using feedforward techniques only

Abstract

A bi-directional isolation scheme is described in which digital data, including clock information, may be communicated bi-directionally across a single isolation barrier without requiring a phase locked loop (PLL) based clock recovery procedure. In this way, the lead-time needed by the receiving circuit to recover the data clock signal may be reduced and the polarity (or 180° phase) ambiguities often associated with PLL-based methods may be avoided.

Claims

1. A bi-directional isolation system for providing an isolated communication channel for a source data signal synchronized by a source clock signal, comprising:

a bi-directional isolation barrier;

a source interface circuit coupled on one side of the isolation barrier and configured to multiplex the source clock signal on the source data signal and to transmit the multiplex signal across the isolation barrier; and

an isolated interface circuit coupled on an opposite side of the isolation barrier and configured to generate from the multiplex signal a recovered data signal and a recovered clock signal synchronized with the source clock signal.

2. The system of claim 1, wherein the source interface circuit multiplexes the source clock signal on the source data signal by summing the source clock signal and the source data signal.

3. The system of claim 2, wherein the source interface circuit is configured to quantize the source data signal and the source clock signal to respective logic levels.

4. The system of claim 3, wherein the source clock signal logic levels span a wider range of values than the source data signal logic levels.

5. The system of claim 1, wherein the isolated interface circuit generates the recovered clock signal by slicing the multiplex signal.

6. The system of claim 5, wherein the isolated interface circuit generates the recovered clock signal by slicing the multiplex signal at an intermediate multiplex signal level.

7. The system of claim 6, wherein the isolated interface circuit generates the recovered clock signal by slicing the multiplex signal at a level between a sum of a low source data signal logic level and a high source clock signal logic level and a sum of a high source data signal logic level and a low source clock signal logic level.

8. The system of claim 5, wherein the isolated interface circuit generates the recovered data signal by slicing a time-delayed version of the multiplex signal.

9. The system of claim 8, wherein the time-delayed version of the multiplex signal is sliced synchronously with the recovered clock signal.

10. The system of claim 8, wherein the time-delayed version of the multiplex signal is sliced at a level greater than a sum of a low source data signal logic level and a high source clock signal logic level.

11. The system of claim 8, wherein the time-delayed version of the multiplex signal is sliced at a level less than a sum of a high source data signal logic level and a low source clock signal logic level.

12. A bi-directional isolation method for providing an isolated communication channel across a bi-directional isolation barrier for a source data signal synchronized by a source clock signal, comprising:

on one side of the isolation barrier, multiplexing the source clock signal on the source data signal and transmitting the multiplex signal across the isolation barrier; and

on an opposite side of the isolation barrier, generating from the multiplex signal a recovered data signal and a recovered clock signal synchronized with the source clock signal.

13. The method of claim 12, wherein the source clock signal is multiplexed on the source data signal by summing the source clock signal and the source data signal.

14. The method of claim 13, further comprising quantizing the source data signal and the source clock signal to respective logic levels.

15. The method of claim 14, wherein the source clock signal logic levels span a wider range of values than the source data signal logic levels.

16. The method of claim 12, further comprising generating the recovered clock signal by slicing the multiplex signal.

17. The method of claim 16, wherein the recovered clock signal is generated by slicing the multiplex signal at an intermediate multiplex signal level.

18. The method of claim 17, wherein the recovered clock signal is generated by slicing the multiplex signal at a level between a sum of a low source data signal logic level and a high source clock signal logic level and a sum of a high source data signal logic level and a low source clock signal logic level.

19. The method of claim 16, wherein the recovered data signal is generated by slicing a time-delayed version of the multiplex signal.

20. The method of claim 19, wherein the time-delayed version of the multiplex signal is sliced synchronously with the recovered clock signal.

21. The method of claim 19, wherein the time-delayed version of the multiplex signal is sliced at a level greater than a sum of a low source data signal logic level and a high source clock signal logic level.

22. The method of claim 19, wherein the time-delayed version of the multiplex signal is sliced at a level less than a sum of a high source data signal logic level and a low source clock signal logic level.