Column address path circuit and method for memory devices having a burst access mode

• US 20040013010A1
• Filed: 04/15/2003
• Published: 01/22/2004
• Est. Priority Date: 03/09/2001
• Status: Active Grant

• Current Assignee: Duc V. Ho
• Original Assignee: Duc V. Ho
• Inventors: Ho, Duc V.
• Granted Patent: US 6,848,040 B2
• Time in Patent Office: Days
• US Class Current: 365/200
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters

Abstract

Column addresses are generated by a burst controller that includes respective latches for the three low-order bits of a column address. The two higher order bits of the latched address bits and their compliments are applied to respective first multiplexers along with respective bits from a burst counter. The first multiplexers apply the latched address bits and their compliments to respective second multiplexers during a first bit of a burst access, and bits from a burst counter during the remaining bits of the burst. The second multiplexers are operable responsive to a control signal to couple either the latched address bits or their compliments to respective outputs for use as an internal address. The control signal is generated by an adder logic circuit that receives the two low-order bits of the column address. The adder logic circuit processes the column address bits at the same time the address bits are being coupled through the second multiplexer to the first multiplexer as a function of the correct relationship between the internal address bits and the external address bits.

Claims

1. A burst controller, comprising

a first multiplexer having a first input terminal coupled to receive a first address bit corresponding to an external column address bit and a second input terminal coupled to receive a second address bit corresponding to a compliment of the external column address bit, the multiplexer having a control input and being operable to couple one of the received address bits to an output terminal responsive to a control signal applied to the control input;

and

a logic circuit processing a third address bit corresponding to the external column address bit, the logic circuit being operable to generate the control signal as a function of the processing of the third control signal, the logic circuit having an output terminal coupled to the control input of the multiplexer to cause the multiplexer to couple one of the received address bits to the output terminal of the multiplexer.

2. The burst controller of claim 1, further comprising an address latch having an input terminal and an output terminal coupled to one of the input terminals of the multiplexer, the address latch being operable to store the external address bit and to apply the stored address bit to the multiplexer.

3. The burst controller of claim 1, further comprising:

a burst counter structured to generated a plurality of bits corresponding to an address count; and

a second multiplexer having first and second input terminals coupled to receive the first and second address bits, respectively, and a third input terminal coupled to the burst counter to receive one of the address count bits, the second multiplexer further including a pair of output terminals coupled to respective ones of the input terminals of the first multiplexer, the second multiplexer being operable to couple the first and second input terminals to respective ones of the first and second input terminals of the first multiplexer in a first state of the second multiplexer, and to couple the third input terminal to one of the first and second input terminals of the first multiplexer in a second state of the second multiplexer.

4. The burst controller of claim 1, wherein the logic circuit comprises an adder logic circuit receiving the third address bit and a fourth address bit corresponding to an external column address bit that is different from the external column address bit to which the third address bit corresponds, the adder logic circuit being structured to generate the control signal as a function of the processing of the third and fourth address bits.

5. The burst controller of claim 1, wherein the logic circuit comprises an adder logic circuit receiving a mode signal having a first state indicative of a serial mode of operation and a second state indicative of an interleaved mode of operation, the adder logic circuit being structured to generate the control signal as a function of the state of the mode signal.

6. The burst controller of claim 1, wherein the logic circuit comprises an adder logic circuit receiving a burst length signal having a first state indicative of a burst of address signals having a first length and a second state indicative of a burst of address signals having a second length, the adder logic circuit being structured to generate the control signal as a function of the state of the burst length signal.

7. A burst controller, comprising

a first address latch receiving a first external column address, the first address latch being structured to store the first external column address and to couple the stored address to an output terminal;

a second address latch receiving a second external column address, the second address latch being structured to store the second external column address and to couple the stored address to an output terminal;

a third address latch receiving a third external column address, the third address latch being structured to store the third external column address and to couple the stored address to an output terminal;

a burst counter generating a plurality of count bits corresponding to a counted column address;

a first multiplexer having first and second input terminals, the first input terminal being coupled to the output terminal of the second address latch to receive the stored second external column address, and the second input terminal being coupled to the output terminal of the second address latch through an inverter to receive the compliment of the stored second external column address, the first multiplexer further including a third input terminal coupled to the burst counter to receive one of the count bits, the first multiplexer having a control input and being operable to couple the first and second input terminals to respective first and second output terminals responsive to a first state of the control signal, and to couple the third input terminal to one of the first and second output terminals responsive to a second state of the control signal;

a second multiplexer having first and second input terminals, the first input terminal being coupled to the output terminal of the third address latch to receive the stored third external column address, and the second input terminal being coupled to the output terminal of the third address latch through an inverter to receive the compliment of the stored third external column address, the second multiplexer further including a third input terminal coupled to the burst counter to receive one of the count bits, the second multiplexer having a control input and being operable to couple the first and second input terminals to respective first and second output terminals responsive to a first state of the control signal, and to couple the third input terminal to one of the first and second output terminals responsive to a second state of the control signal;

a third multiplexer having first and second input terminals coupled to the first and second output terminals of the first multiplexer, the third multiplexer having a control input and being operable to couple the first input terminal to an output terminal responsive to a first state of the control signal, and to couple the second input terminal to the output terminal responsive to a second state of the control signal;

a fourth multiplexer having first and second input terminals coupled to the first and second output terminals of the second multiplexer, the fourth multiplexer having a control input and being operable to couple the first input terminal to an output terminal responsive to a first state of the control signal, and to couple the second input terminal to the output terminal responsive to a second state of the control signal; and

a logic circuit having a first input coupled to the output terminal of the first address latch to receive the stored first external column address and a second input coupled to the output terminal of the second address latch to receive the stored second external column address, the logic circuit having an output terminal coupled to the control input of the third multiplexer and an output coupled to the control input of the fourth multiplexer, the logic circuit being operable to generate first and second states of the control signal as a function of the processing of the stored first and second external column addresses.

8. The burst controller of claim 7, wherein the logic circuit comprises an adder logic circuit receiving a mode signal having a first state indicative of a serial mode of operation and a second state indicative of an interleaved mode of operation, the adder logic circuit being structured to generate the control signal as a function of the state of the mode signal.

9. The burst controller of claim 7, wherein the logic circuit comprises an adder logic circuit receiving a burst length signal having a first state indicative of a burst of address signals having a first length and a second state indicative of a burst of address signals having a second length, the adder logic circuit being structured to generate the control signal as a function of the state of the burst length signal.

10. A memory device, comprising:

at least one array of memory cells arranged in rows and columns, each of the rows having a row line and each of the columns having a pair of complementary digit lines;

a row address circuit coupled to the address bus for activating a row line corresponding to a row address coupled to the row address circuit through the address bus;

a column address circuit coupled to the address bus for receiving an external column address and for selecting a column of the memory array corresponding to an internal column address; and

a burst controller coupled to the address bus and to the column address circuit, the burst controller comprising;

a first multiplexer having a first input terminal coupled to the column address circuit to receive a first address bit corresponding to the external column address bit and a second input terminal coupled to receive a second address bit corresponding to a compliment of the external column address bit, the multiplexer having a control input and being operable to couple one of the received address bits to an output terminal responsive to a control signal applied to the control input, the output terminal being coupled to the memory array to provide the internal column address; and

a logic circuit processing a third address bit corresponding to the external column address bit, the logic circuit being operable to generate the control signal as a function of the processing of the third control signal, the logic circuit having an output terminal coupled to the control input of the multiplexer to cause the multiplexer to couple one of the received address bits to the output terminal of the multiplexer.

11. The memory device of claim 10, further comprising an address latch having an input terminal and an output terminal coupled to one of the input terminals of the multiplexer, the address latch being operable to store the external address bit and apply the stored address bit to the multiplexer.

12. The memory device of claim 10, further comprising:

a burst counter structured to generated a plurality of bits corresponding to an address count; and

a second multiplexer having first and second input terminals coupled to receive the first and second address bits, respectively, and a third input terminal coupled to the burst counter to receive one of the address count bits, the second multiplexer further including a pair of output terminals coupled to respective ones of the input terminals of the first multiplexer, the second multiplexer being operable to couple the first and second input terminals to respective ones of the first and second input terminals of the first multiplexer in a first state of the second multiplexer, and to couple the third input terminal to one of the first and second input terminals of the first multiplexer in a second state of the second multiplexer.

13. The memory device of claim 10, wherein the logic circuit comprises an adder logic circuit receiving the third address bit and a fourth address bit corresponding to an external column address bit that is different from the external column address bit to which the third address bit corresponds, the adder logic circuit being structured to generate the control signal as a function of the processing of the third and fourth address bits.

14. The memory device of claim 10, wherein the logic circuit comprises an adder logic circuit receiving a mode signal having a first state indicative of a serial mode of operation and a second state indicative of an interleaved mode of operation, the adder logic circuit being structured to generate the control signal as a function of the state of the mode signal.

15. The memory device of claim 10, wherein the logic circuit comprises an adder logic circuit receiving a burst length signal having a first state indicative of a burst of address signals having a first length and a second state indicative of a burst of address signals having a second length, the adder logic circuit being structured to generate the control signal as a function of the state of the burst length signal.

16. A memory device, comprising:

at least one array of memory cells arranged in rows and columns, each of the rows having a row line and each of the columns having a pair of complementary digit lines;

a row address circuit coupled to the address bus for activating a row line corresponding to a row address coupled to the row address circuit through the address bus;

a column address circuit coupled to the address bus for selecting a column for a memory access that corresponds to a column address coupled to the column address circuit through the address bus; and

a column address circuit coupled to the address bus for receiving an external column address and for selecting a column of the memory array corresponding to an internal column address; and

a burst controller coupled to the address bus and to the column address circuit, the burst controller comprising;

a first address latch receiving a first external column address, the first address latch being structured to store the first external column address and to couple the stored address to an output terminal;

a second address latch receiving a second external column address, the second address latch being structured to store the second external column address and to couple the stored address to an output terminal;

a third address latch receiving a third external column address, the third address latch being structured to store the third external column address and to couple the stored address to an output terminal;

a burst counter generating a plurality of count bits corresponding to a counted column address;

a first multiplexer having first and second input terminals, the first input terminal being coupled to the output terminal of the second address latch to receive the stored second external column address, and the second input terminal being coupled to the output terminal of the second address latch through an inverter to receive the compliment of the stored second external column address, the first multiplexer further including a third input terminal coupled to the burst counter to receive one of the count bits, the first multiplexer having a control input and being operable to couple the first and second input terminals to respective first and second output terminals responsive to a first state of the control signal, and to couple the third input terminal to one of the first and second output terminals responsive to a second state of the control signal;

a second multiplexer having first and second input terminals, the first input terminal being coupled to the output terminal of the third address latch to receive the stored third external column address, and the second input terminal being coupled to the output terminal of the third address latch through an inverter to receive the compliment of the stored third external column address, the second multiplexer further including a third input terminal coupled to the burst counter to receive one of the count bits, the second multiplexer having a control input and being operable to couple the first and second input terminals to respective first and second output terminals responsive to a first state of the control signal, and to couple the third input terminal to one of the first and second output terminals responsive to a second state of the control signal;

a third multiplexer having first and second input terminals coupled to the first and second output terminals of the first multiplexer, the third multiplexer having a control input and being operable to couple the first input terminal to an output terminal responsive to a first state of the control signal, and to couple the second input terminal to the output terminal responsive to a second state of the control signal, the output terminal being coupled to the memory array to provide the internal column address;

a fourth multiplexer having first and second input terminals coupled to the first and second output terminals of the second multiplexer, the fourth multiplexer having a control input and being operable to couple the first input terminal to an output terminal responsive to a first state of the control signal, and to couple the second input terminal to the output terminal responsive to a second state of the control signal, the output terminal being coupled to the memory array to provide the internal column address; and

a logic circuit having a first input coupled to the output terminal of the first address latch to receive the stored first external column address and a second input coupled to the output terminal of the second address latch to receive the stored second external column address, the logic circuit having an output terminal coupled to the control input of the third multiplexer and an output coupled to the control input of the fourth multiplexer, the logic circuit being operable to generate first and second states of the control signal as a function of the processing of the stored first and second external column addresses.

17. The memory device of claim 16, wherein the logic circuit comprises an adder logic circuit receiving a mode signal having a first state indicative of a serial mode of operation and a second state indicative of an interleaved mode of operation, the adder logic circuit being structured to generate the control signal as a function of the state of the mode signal.

18. The memory device of claim 16, wherein the logic circuit comprises an adder logic circuit receiving a burst length signal having a first state indicative of a burst of address signals having a first length and a second state indicative of a burst of address signals having a second length, the adder logic circuit being structured to generate the control signal as a function of the state of the burst length signal.

19. A computer system, comprising:

a processor having a processor bus;

an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system;

an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and

a memory device coupled to the processor through the processor bus, the memory device comprising;

at least one array of memory cells arranged in rows and columns, each of the rows having a row line and each of the columns having a pair of complementary digit lines;

a row address circuit coupled to the address bus for activating a row line corresponding to a row address coupled to the row address circuit through the address bus;

a column address circuit coupled to the address bus for receiving an external column address and for selecting a column of the memory array corresponding to an internal column address; and

a burst controller coupled to the address bus and to the column address circuit, the burst controller comprising;

a first multiplexer having a first input terminal coupled to the column address circuit to receive a first address bit corresponding to the external column address bit and a second input terminal coupled to receive a second address bit corresponding to a compliment of the external column address bit, the multiplexer having a control input and being operable to couple one of the received address bits to an output terminal responsive to a control signal applied to the control input, the output terminal being coupled to the memory array to provide the internal column address; and

a logic circuit processing a third address bit corresponding to the external column address bit, the logic circuit being operable to generate the control signal as a function of the processing of the third control signal, the logic circuit having an output terminal coupled to the control input of the multiplexer to cause the multiplexer to couple one of the received address bits to the output terminal of the multiplexer.

20. The computer system of claim 19, further comprising an address latch having an input terminal and an output terminal coupled to one of the input terminals of the multiplexer, the address latch being operable to store the external address bit and apply the stored address bit to the multiplexer.

21. The computer system of claim 19, further comprising:

a burst counter structured to generated a plurality of bits corresponding to an address count; and

a second multiplexer having first and second input terminals coupled to receive the first and second address bits, respectively, and a third input terminal coupled to the burst counter to receive one of the address count bits, the second multiplexer further including a pair of output terminals coupled to respective ones of the input terminals of the first multiplexer, the second multiplexer being operable to couple the first and second input terminals to respective ones of the first and second input terminals of the first multiplexer in a first state of the second multiplexer, and to couple the third input terminal to one of the first and second input terminals of the first multiplexer in a second state of the second multiplexer.

22. The computer system of claim 19, wherein the logic circuit comprises an adder logic circuit receiving the third address bit and a fourth address bit corresponding to an external column address bit that is different from the external column address bit to which the third address bit corresponds, the adder logic circuit being structured to generate the control signal as a function of the processing of the third and fourth address bits.

23. The computer system of claim 19, wherein the logic circuit comprises an adder logic circuit receiving a mode signal having a first state indicative of a serial mode of operation and a second state indicative of an interleaved mode of operation, the adder logic circuit being structured to generate the control signal as a function of the state of the mode signal.

24. The computer system of claim 19, wherein the logic circuit comprises an adder logic circuit receiving a burst length signal having a first state indicative of a burst of address signals having a first length and a second state indicative of a burst of address signals having a second length, the adder logic circuit being structured to generate the control signal as a function of the state of the burst length signal.

25. A method of generating a bit of an internal column address corresponding to an external column address, the method comprising:

coupling a bit of the external address and its complement to a selection circuit through a first signal path;

while the external address bit and its complement are being coupled through the first signal path, processing the external address bit to determine the relationship between the internal column address bit and the external column address bit, and generating a control signal corresponding to the determined relationship; and

coupling the control signal to the selection circuit to cause the selection circuit to select either the bit of the external address or its complement as the internal address bit based on the control signal.

26. The method of claim 25, wherein the act of coupling a bit of the external address and its complement to a selection circuit through a first signal path comprises:

receiving and storing the external address bit;

applying the stored external address bit to the selection circuit;

inverting the stored external address bit; and

applying the inverted stored external address bit to the selection circuit.

27. The method of claim 25, wherein the act of processing the external address bit to determine the relationship between the internal column address bit and the external column address bit further comprises processing the external address bit in one manner responsive to operation in one mode and processing the external address bit in a different manner responsive to operation in a different mode.

28. The method of claim 25, wherein the act of coupling a bit of the external address and its complement to the selection circuit comprises:

applying a bit of a counter to an input of a multiplexer placed in the first signal path,

applying a bit of the external address and its complement to respective inputs of the multiplexer; and

coupling one of the inputs of the multiplexer to the selection circuit.

29. A method of generating a bit of an internal column address corresponding to an external column address, the method comprising:

processing the external address bit to determine the relationship between the internal column address bit and the external column address bit;

coupling a bit of the external address and its complement to a selection circuit through a first signal path while the external address bit is being processed; and

causing the selection circuit to select either the bit of the external address or its complement as the internal address bit based on the processing of the external address bit.

30. The method of claim 29, wherein the act of coupling a bit of the external address and its complement to a selection circuit through a first signal path comprises:

receiving and storing the external address bit;

applying the stored external address bit to the selection circuit;

inverting the stored external address bit; and

applying the inverted stored external address bit to the selection circuit.

31. The method of claim 29, wherein the act of processing the external address bit to determine the relationship between the internal column address bit and the external column address bit further comprises processing the external address bit in one manner responsive to operation in one mode and processing the external address bit in a different manner responsive to operation in a different mode.

32. The method of claim 29, wherein the act of coupling a bit of the external address and its complement to the selection circuit comprises:

applying a bit of a counter to an input of a multiplexer placed in the first signal path,

applying a bit of the external address and its complement to respective inputs of the multiplexer; and

coupling one of the inputs of the multiplexer to the selection circuit.