Bit stream conditioning circuit having adjustable input sensitivity
First Claim
1. A high-speed serial bit stream interface that communicatively couples a line side media to a communication Application Specific Integrate Circuit (ASIC), the high-speed serial bit stream interface comprising:
- a line side interface that communicatively couples to the line side media, that receives an RX signal therefrom, and that transmits a TX signal thereto;
a board side interface that communicatively couples to the communication ASIC, that receives the TX signal therefrom, and that transmits the RX signal thereto;
an RX signal conditioning circuit communicatively coupled between an RX portion of the line side interface and an RX portion of the board side interface;
a TX signal conditioning circuit communicatively coupled between a TX portion of the line side interface and a TX portion of the board side interface;
wherein the RX signal conditioning circuit and the TX signal conditioning circuit operate on the RX signal and the TX signal, respectively, and each comprise;
a limiting amplifier that receives the respective serviced signal and that controllably amplifies the respective serviced signal to produce the respective serviced signal in a desired output range; and
a clock and data recovery circuit communicatively coupled to the output of the limiting amplifier, wherein the clock and data recover circuit receives, recovers, and reclocks the respective serviced signal; and
wherein the limiting amplifier servicing the RX signal and the limiting amplifier servicing the TX signal are separately controlled to produce respective serviced signals in the desired output range.
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Accused Products
Abstract
A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The limiting amplifier applies respective gains to the RX path and to the TX path that are based upon respective dynamic ranges of the incoming signals.
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Citations
22 Claims
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1. A high-speed serial bit stream interface that communicatively couples a line side media to a communication Application Specific Integrate Circuit (ASIC), the high-speed serial bit stream interface comprising:
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a line side interface that communicatively couples to the line side media, that receives an RX signal therefrom, and that transmits a TX signal thereto;
a board side interface that communicatively couples to the communication ASIC, that receives the TX signal therefrom, and that transmits the RX signal thereto;
an RX signal conditioning circuit communicatively coupled between an RX portion of the line side interface and an RX portion of the board side interface;
a TX signal conditioning circuit communicatively coupled between a TX portion of the line side interface and a TX portion of the board side interface;
wherein the RX signal conditioning circuit and the TX signal conditioning circuit operate on the RX signal and the TX signal, respectively, and each comprise;
a limiting amplifier that receives the respective serviced signal and that controllably amplifies the respective serviced signal to produce the respective serviced signal in a desired output range; and
a clock and data recovery circuit communicatively coupled to the output of the limiting amplifier, wherein the clock and data recover circuit receives, recovers, and reclocks the respective serviced signal; and
wherein the limiting amplifier servicing the RX signal and the limiting amplifier servicing the TX signal are separately controlled to produce respective serviced signals in the desired output range. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A high-speed serial bit stream conditioning circuit comprising:
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an equalizer that receives a high-speed serial bit stream and that spectrally shapes the high-speed serial bit stream to produce an equalized high-speed serial bit stream;
a limiting amplifier operably coupled to the output of the equalizer that receives the equalized high-speed serial bit stream and that controllably amplifies the equalized high-speed serial bit stream to produce the equalized high-speed serial bit stream in a desired output range; and
a clock and data recovery circuit operably coupled to the output of the limiting amplifier that recovers the equalized high-speed bit stream to produce an output high-speed serial bit stream. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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19. A method for recovering a high-speed serial bit stream comprising:
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receiving the high-speed serial bit stream;
amplifying the high-speed serial bit stream using a gain setting corresponding to a dynamic range of the high-speed serial bit stream as received; and
recovering the equalized high-speed bit stream to produce an output high-speed serial bit stream. - View Dependent Claims (20, 21, 22)
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Specification