Stable PD-SOI devices and methods
First Claim
1. A partially depleted silicon-on-insulator structure, comprising:
- a substrate;
an oxide insulation layer disposed above the silicon substrate;
an active region formed above the oxide insulation layer, including;
a first silicon (Si) epitaxial layer disposed above the oxide insulation layer, the first Si epitaxial layer including a number of recombination centers;
a silicon germanium (Si—
Ge) epitaxial layer disposed above the first Si epitaxial layer, the Si—
Ge epitaxial layer including a number of recombination centers; and
a second Si epitaxial layer disposed above the Si—
Ge epitaxial layer;
at least one source region and at least one drain region formed in the active region, the recombination centers in the Si—
Ge epitaxial layer including recombination centers in the source region and the drain region;
a gate oxide layer formed above the active region to define a channel region in the active region between the source region and the drain region;
a gate formed above the gate oxide layer;
a metal silicide layer formed above the second Si epitaxial layer; and
a lateral metal Schottky layer selectively formed above the second Si epitaxial layer to contact the source region and the active region.
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Accused Products
Abstract
One aspect of the present subject matter relates to a partially depleted silicon-on-insulator structure. The structure includes a well region formed above an oxide insulation layer. In various embodiments, the well region is a multilayer epitaxy that includes a silicon germanium (Si—Ge) layer. In various embodiments, the well region includes a number of recombination centers between the Si—Ge layer, and the insulation layer. A source region, a drain region, a gate oxide layer, and a gate are formed. In various embodiments, the Si—Ge layer includes a number of recombination centers in the source/drain regions. In various embodiments, a metal silicide layer and a lateral metal Schottky layer are formed above the well region to contact the source region and the well region. Other aspects are provided herein.
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Citations
146 Claims
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1. A partially depleted silicon-on-insulator structure, comprising:
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a substrate;
an oxide insulation layer disposed above the silicon substrate;
an active region formed above the oxide insulation layer, including;
a first silicon (Si) epitaxial layer disposed above the oxide insulation layer, the first Si epitaxial layer including a number of recombination centers;
a silicon germanium (Si—
Ge) epitaxial layer disposed above the first Si epitaxial layer, the Si—
Ge epitaxial layer including a number of recombination centers; and
a second Si epitaxial layer disposed above the Si—
Ge epitaxial layer;
at least one source region and at least one drain region formed in the active region, the recombination centers in the Si—
Ge epitaxial layer including recombination centers in the source region and the drain region;
a gate oxide layer formed above the active region to define a channel region in the active region between the source region and the drain region;
a gate formed above the gate oxide layer;
a metal silicide layer formed above the second Si epitaxial layer; and
a lateral metal Schottky layer selectively formed above the second Si epitaxial layer to contact the source region and the active region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A partially depleted silicon-on-insulator structure, comprising:
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a substrate;
an oxide insulation layer disposed above the silicon substrate;
an active region formed above the oxide insulation layer, the active region including a silicon germanium (Si—
Ge) epitaxial layer, the Si—
Ge epitaxial layer including a number of recombination centers;
at least one source region and at least one drain region formed in the active region, the recombination centers in the Si—
Ge epitaxial layer including recombination centers in the source region and the drain region;
a gate oxide layer formed above the active region to define a channel region in the active region between the source region and the drain region; and
a gate formed above the gate oxide layer. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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22. A partially depleted silicon-on-insulator structure, comprising:
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a substrate;
an oxide insulation layer disposed above the silicon substrate;
an active region formed above the oxide insulation layer, including a number of recombination centers positioned near the oxide insulator layer;
at least one source region and at least one drain region formed in the active region;
a gate oxide layer formed above the active region to define a channel region in the active region between the source region and the drain region;
a gate formed above the gate oxide layer; and
a lateral metal Schottky layer selectively formed to contact the source region and the active region. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
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35. A partially depleted silicon-on-insulator structure, comprising:
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a substrate;
an oxide insulation layer disposed above the silicon substrate;
an active region formed above the oxide insulation layer, the active region including a silicon germanium (Si—
Ge) epitaxial layer;
at least one source region and at least one drain region formed in the active region;
a gate oxide layer formed above the active region to define a channel region in the active region between the source region and the drain region;
a gate formed above the gate oxide layer; and
a lateral metal Schottky layer selectively formed to contact the source region and the active region. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46)
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47. A partially depleted silicon-on-insulator structure, comprising:
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a substrate;
an oxide insulation layer disposed above the silicon substrate;
an active region formed above the oxide insulation layer, the active region including a silicon germanium (Si—
Ge) epitaxial layer, the Si—
Ge epitaxial layer including a number of recombination centers;
at least one source region and at least one drain region formed in the active region, the recombination centers in the Si—
Ge epitaxial layer including recombination centers in the source region and the drain region;
a gate oxide layer formed above the active region to define a channel region in the active region between the source region and the drain region;
a gate formed above the gate oxide layer; and
a lateral metal Schottky layer selectively formed to contact the source region and the active region. - View Dependent Claims (48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58)
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59. A partially depleted silicon-on-insulator structure, comprising:
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a substrate;
an oxide insulation layer disposed above the silicon substrate;
an active region formed above the oxide insulation layer, the active region including a silicon germanium (Si—
Ge) epitaxial layer, the active region including a number of recombination centers between the Si—
Ge epitaxial and the oxide insulation layer;
at least one source region and at least one drain region formed in the active region;
a gate oxide layer formed above the active region to define a channel region in the active region between the source region and the drain region; and
a gate formed above the gate oxide layer. - View Dependent Claims (60, 61, 62, 63, 64, 65, 66, 67)
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68. A partially depleted silicon-on-insulator structure, comprising:
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a substrate;
an oxide insulation layer disposed above the silicon substrate;
an active region formed on the oxide insulation layer, the active region including a silicon germanium (Si—
Ge) epitaxial layer, the active region including a number of recombination centers between the Si—
Ge epitaxial layer and the oxide insulation layer, the Si—
Ge epitaxial layer including a number of recombination centers;
at least one source region and at least one drain region formed in the active region, the recombination centers in the Si—
Ge epitaxial layer including recombination centers in the source region and the drain region;
a gate oxide layer formed above the active region to define a channel region in the active region between the source region and the drain region; and
a gate formed above the gate oxide layer. - View Dependent Claims (69, 70, 71, 72, 73, 74, 75)
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76. A method of fabricating a silicon-on-insulator (SOI) structure, comprising:
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forming a multilayer epitaxy on an oxide insulating layer, including forming a silicon germanium (Si—
Ge) epitaxial layer;
providing shallow trench isolation (STI) in the multilayer epitaxy to form an SOI active region;
forming recombination centers in the multilayer epitaxy near the oxide insulating layer below the Si—
Ge epitaxial layer;
forming a number of wells in the multilayer epitaxy;
performing processing steps for forming active devices in the multilayer epitaxy;
forming recombination centers in the Si—
Ge epitaxial layer;
forming source/drain regions for the active devices;
forming a metal silicide over the active region of the active devices; and
forming a lateral Schottky on the metal silicide to contact a source region and the SOI active region. - View Dependent Claims (77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88)
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89. A method of fabricating a silicon-on-insulator (SOI) structure, comprising:
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forming a multilayer epitaxy on an oxide insulating layer, including forming a silicon germanium (Si—
Ge) epitaxial layer;
providing shallow trench isolation (STI) in the multilayer epitaxy to form an SOI active region;
forming a number of wells in the multilayer epitaxy;
performing processing steps for forming active devices in the multilayer epitaxy, each of the active devices being formed with a gate;
forming recombination centers in the Si—
Ge epitaxial layer; and
forming source/drain regions for the active devices. - View Dependent Claims (90, 91, 92, 93, 94)
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95. A method of fabricating a silicon-on-insulator (SOI) structure, comprising:
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forming a body layer on an oxide insulating layer;
providing shallow trench isolation (STI) in the body layer to form an SOI active region;
forming recombination centers in the body layer near the oxide insulating layer;
forming a number of wells in the body layer;
performing processing steps for forming active devices in the body layer, each of the active devices being formed with a gate;
forming source/drain regions for the active devices;
forming a metal silicide over the gates of the active devices; and
forming a lateral Schottky on the metal silicide. - View Dependent Claims (96, 97, 98, 99, 100, 101, 102, 103, 104)
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105. A method of fabricating a silicon-on-insulator (SOI) structure, comprising:
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forming an epitaxy on an oxide insulating layer, including forming a silicon germanium (Si—
Ge) epitaxial layer;
providing shallow trench isolation (STI) in the epitaxy to form an SOI active region;
forming a number of wells in the epitaxy;
performing processing steps for forming active devices in the epitaxy, each of the active devices being formed with a gate;
forming source/drain regions for the active devices;
forming a metal silicide over the gates of the active devices; and
forming a lateral Schottky on the metal silicide. - View Dependent Claims (106, 107, 108, 109, 110, 111, 112, 113, 114, 115)
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116. A method of fabricating a silicon-on-insulator (SOI) structure, comprising:
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forming an epitaxy on an oxide insulating layer, including forming a silicon germanium (Si—
Ge) epitaxial layer;
providing shallow trench isolation (STI) in the epitaxy to form an SOI active region;
forming a number of wells in the epitaxy;
performing processing steps for forming active devices in the epitaxy, each of the active devices being formed with a gate;
forming recombination centers in the Si—
Ge epitaxial layer;
forming source/drain regions for the active devices;
forming a metal silicide over the gates of the active devices; and
forming a lateral Schottky on the metal silicide. - View Dependent Claims (117, 118, 119, 120, 121, 122, 123, 124, 125, 126)
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127. A method of fabricating a silicon-on-insulator (SOI) structure, comprising:
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forming a multilayer epitaxy on an oxide insulating layer, including forming a silicon germanium (Si—
Ge) epitaxial layer;
providing shallow trench isolation (STI) in the multilayer epitaxy to form an SOI active region;
forming recombination centers in the multilayer epitaxy below the Si—
Ge epitaxial layer near the oxide insulating layer;
forming a number of wells in the multilayer epitaxy;
performing processing steps for forming active devices in the multilayer epitaxy, each of the active devices being formed with a gate;
forming recombination centers in the Si—
Ge epitaxial layer; and
forming source/drain regions for the active devices. - View Dependent Claims (128, 129, 130, 131, 132)
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133. A semiconductor chip, comprising:
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a silicon substrate;
an oxide insulation layer disposed above the silicon substrate;
an n−
type body layer disposed above a second portion of the oxide insulation layer, the n−
type body layer including a silicon germanium (Si—
Ge) epitaxial layer;
a PFET device in association with the n−
type body layer, the PFET device including a source region and a silicided lateral Schottky layer in contact with the source region and the n−
type body layer;
a p−
type body layer disposed above a first portion of the oxide insulation layer, the p−
type body layer including a silicon germanium (Si—
Ge) epitaxial layer; and
an NFET device in association with the p−
type body layer, the NFET device including a source region and both a silicide metal layer and a metal lateral Schottky layer in contact with the source region and the p−
type body layer. - View Dependent Claims (134, 135, 136, 137, 138)
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139. A semiconductor chip, comprising:
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a silicon substrate;
an oxide insulation layer disposed above the silicon substrate;
an n−
type body layer disposed above a second portion of the oxide insulation layer, the n−
type body layer including a silicon germanium (Si—
Ge) epitaxial layer, the Si—
Ge epitaxial layer including a number of recombination centers, the n−
type body layer including a number of recombination centers between the Si—
Ge epitaxial layer and the oxide insulation layer;
a PFET device in association with the n−
type body layer;
a p−
type body layer disposed above a first portion of the oxide insulation layer, the p−
type body layer including a silicon germanium (Si—
Ge) epitaxial layer, the Si—
Ge epitaxial layer including a number of recombination centers, the p−
type body layer including a number of recombination centers between the Si—
Ge epitaxial layer and the oxide insulation layer; and
an NFET device in association with the p−
type body layer. - View Dependent Claims (140, 141)
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142. An electronic system, comprising:
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a processor; and
a memory device coupled to the processor, wherein at least one of the processor and the memory device includes a semiconductor chip, comprising;
a silicon substrate;
an oxide insulation layer disposed above the silicon substrate;
an n−
type body layer disposed above a second portion of the oxide insulation layer, the n−
type body layer including a silicon germanium (Si—
Ge) epitaxial layer;
a PFET device in association with the n−
type body layer, the PFET device including a source region and a silicided lateral Schottky layer in contact with the source region and the −
type body layer;
a p−
type body layer disposed above a first portion of the oxide insulation layer, the p−
type body layer including a silicon germanium (Si—
Ge) epitaxial layer; and
an NFET device in association with the p−
type body layer, the NFET device including a source region and a metal lateral Schottky layer in contact with the source region and the p−
type body layer. - View Dependent Claims (143, 144)
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145. An electronic system, comprising:
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a processor; and
a memory device coupled to the processor, wherein at least one of the processor and the memory device includes a semiconductor chip, comprising;
a silicon substrate;
an oxide insulation layer disposed above the silicon substrate;
an n−
type body layer disposed above a second portion of the oxide insulation layer, the n−
type body layer including a silicon germanium (Si—
Ge) epitaxial layer, the Si—
Ge epitaxial layer including a number of recombination centers, the n−
type body layer including a number of recombination centers between the Si—
Ge epitaxial layer and the oxide insulation layer;
a PFET device in association with the n−
type body layer;
a p−
type body layer disposed above a first portion of the oxide insulation layer, the p−
type body layer including a silicon germanium (Si—
Ge) epitaxial layer, the Si—
Ge epitaxial layer including a number of recombination centers, the p−
type body layer including a number of recombination centers between the Si—
Ge epitaxial layer and the oxide insulation layer; and
an NFET device in association with the p−
type body layer. - View Dependent Claims (146)
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Specification