Multiplier array processing system with enhanced utilization at lower precision
First Claim
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1. A multiplier processing system for performing a group-multiply-and-sum instruction, said system comprising:
- means for partitioning each of a plurality of operands into a plurality of symbols, said operands and each of said symbols having a predefined bit width;
means for multiplying symbols of a first operand with symbols of a second operand, each of such multiplications producing a product; and
means for adding each product so as to produce a single scalar result, said scalar result capable of being represented by a bit width which is equal to or less than said predefined bit width of said operands without a reduction in the accuracy of said result.
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Abstract
A multiplier array processing system which improves the utilization of the multiplier and adder array for lower-precision arithmetic is described. New instructions are defined which provide for the deployment of additional multiply and add operations as a result of a single instruction, and for the deployment of greater multiply and add operands as the symbol size is decreased.
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Citations
14 Claims
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1. A multiplier processing system for performing a group-multiply-and-sum instruction, said system comprising:
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means for partitioning each of a plurality of operands into a plurality of symbols, said operands and each of said symbols having a predefined bit width;
means for multiplying symbols of a first operand with symbols of a second operand, each of such multiplications producing a product; and
means for adding each product so as to produce a single scalar result, said scalar result capable of being represented by a bit width which is equal to or less than said predefined bit width of said operands without a reduction in the accuracy of said result. - View Dependent Claims (2, 3, 4)
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5. A multiplier processing system for performing a group-multiply-sum-and-add instruction, said system comprising:
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means for partitioning each of a plurality of operands into a plurality of symbols, said operands and each of said symbols having a predefined bit width;
means for multiplying symbols of a first operand with symbols of a second operand, each of such multiplications producing a product; and
means for adding each product and a third operand so as to produce a single scalar result, said scalar result capable of being represented by a bit width which is equal to or less than said predefined bit width of said operands without a reduction in the accuracy of said result. - View Dependent Claims (6, 7)
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8. A method for performing a group-multiply-and-sum instruction, said method comprising the steps of:
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partitioning each of a plurality of operands into a plurality of symbols, said operands and each of said symbols having a predefined bit width;
multiplying symbols of a first operand with symbols of a second operand, each of such multiplications producing a product; and
adding each product so as to produce a single scalar result, said scalar result capable of being represented by a bit width which is equal to or less than said predefined bit width of said operands without a reduction in the accuracy of said result. - View Dependent Claims (9, 10, 11)
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12. A method for performing a group-multiply-sum-and-add instruction, said method comprising the steps of:
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partitioning each of a plurality of operands into a plurality of symbols, said operands and each of said symbols having a predefined bit width;
multiplying symbols of a first operand with symbols of a second operand, each of such multiplications producing a product; and
adding each product and a third operand so as to produce a single scalar result, said scalar result capable of being represented by a bit width which is equal to or less than said predefined bit width of said operands without a reduction in the accuracy of said result. - View Dependent Claims (13, 14)
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Specification