Hardware assisted communication between processors

• US 20040015656A1
• Filed: 07/19/2002
• Published: 01/22/2004
• Est. Priority Date: 07/19/2002
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Cohen, Eugene M., McLean, Scott D., Rust, Robert A.
• Granted Patent: US 6,938,124 B2
• Time in Patent Office: Days
• US Class Current: 711/114
• CPC Class Codes: G06F 11/2089 Redundant storage control functionality
• CPC Class Codes: G06F 3/0617 in relation to availability
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes
• CPC Class Codes: Y10S 707/99953 Recoverability
• CPC Class Codes: Y10S 707/99955 Archiving or backup

Abstract

A method and apparatus performs hardware assisted communication between processors. In response to direction from a first processor, a first coprocessor writes information in a first block of mirrored memory. Mirrored memory is maintained, allowing a second coprocessor to read the information from a second block of mirrored memory. The information is saved in memory accessible to a second processor. The information is accessed by the second processor.

Claims

1. A method of performing hardware assisted communication between processors, comprising:

in response to direction from a first processor, using a first coprocessor to write information in a first block of mirrored memory;

maintaining mirrored memory;

reading, with a second coprocessor, the information from a second block of mirrored memory;

saving the information in memory accessible to a second processor; and

accessing the information with the second processor.

2. The method of claim 1, additionally comprising marshalling the information with the first coprocessor.

3. The method of claim 2, additionally comprising de-marshalling the information with the second coprocessor.

4. The method of claim 3, wherein accessing the information with the second processor comprises using dispatcher code resident within operating system code executed by the second processor.

5. The method of claim 4, additionally comprising:

configuring the second coprocessor to be a queue producer;

configuring the second processor to be a queue consumer; and

configuring a queue to allow the second coprocessor to write to the queue and to allow the second processor to read from the queue.

6. A method of configuring a plurality of groups, each group containing a processor, a coprocessor and an ASIC, to share work, the method comprising:

transferring information between coprocessors through the ASIC with which each coprocessor is grouped, using a bus over which the ASICs are connected;

for each group, configuring a single producer/single consumer queue, wherein the coprocessor is the single producer and the processor is the single consumer;

removing information from the single producer/single consumer queue; and

processing the information using software configured for operation on each processor.

7. The method of claim 6, wherein removing work from the queue comprises:

maintaining mirrored memory by passing information between a plurality of ASICs, wherein each ASIC is associated with each of a plurality of sections of the mirrored memory; and

transferring information between coprocessors using mirrored memory, wherein the information is marshaled before being saved into a first section of mirrored memory by a first coprocessor and de-marshaled after being read from a second section of mirrored memory by a second coprocessor.

8. The method of claim 6, wherein the software configured for operation on each processor is selected from among a group comprising:

front code, configured to control the operation of input/output processors;

middle code configured to control operation of a RAID device; and

back code configured to control disk drive operation.

9. A processor-readable medium, comprising processor-executable instructions for sharing work between remotely located first and second processors, the processor-executable instructions comprising processor-executable instructions for:

issuing a command from the first processor to a first coprocessor using a circular buffer, wherein the command comprises an address and a command type;

marshalling information, using the first coprocessor, associated with the address and according to the command type;

copying marshaled information, using the first coprocessor, into a first block of mirrored memory;

notifying a second coprocessor that a de-marshalling job is available;

reading, from a second block of mirrored memory, the de-marshalling job into the second coprocessor;

performing the de-marshalling job with the second coprocessor to obtain de-marshaled information; and

writing the de-marshaled information to a queue, to provide information to the second processor on an available job.

10. A processor-readable medium as recited in claim 9, wherein writing the de-marshaled information to the queue comprises placing information on the available job into local memory used by an operating system configured for operation by the second processor.

11. A processor-readable medium as recited in claim 9, wherein writing the de-marshaled information to the queue comprises placing information on the available job into local memory where it will be accessed by dispatcher code resident within an operating system configured for operation by the second processor.

12. A processor-readable medium as recited in claim 9, wherein issuing a command from the first processor to the first coprocessor comprises further instructions for:

pointing to data to be sent to the second processor; and

indicating a type of task to be performed.

13. A processor-readable medium as recited in claim 9, wherein copying marshaled memory comprises further instructions for:

writing to a circular buffer configured within mirrored memory; and

de-allocating memory within the circular buffer after the remote coprocessor has read the de-marshalling job.

14. A processor-readable medium as recited in claim 9, comprising further instructions for:

notifying the first processor of command progress only after completion by the second processor.

15. A RAID system, comprising:

a plurality of disks;

a plurality of controller cards, each controller card configured for management of disk and client I/O, each controller card comprising;

local memory;

a processor, in communication with the local memory;

a single processor/single consumer queue, defined in the local memory, and configured to be emptied by the processor; and

an assist engine, to transfer work to the queue, the assist engine comprising;

mirrored memory, comprising a local mirrored memory block and a local array ASIC to maintain the local mirrored memory block with respect to mirrored memory blocks on other controller cards; and

a coprocessor, configured to marshal and write information to the local mirrored memory block and to read and de-marshal information obtained from the local mirrored memory block.

16. The RAID system of claim 15, additionally comprising software configured for operation on the processor, comprising:

front code, configured to control the operation of input/output processors;

middle code configured to control operation of the RAID system; and

back code configured to control disk drive operation.

17. The RAID system of claim 16, wherein the queue is configured to be emptied by dispatcher code, resident in an operating system run by the processor, which is configured to transfer information from the queue to the processor.

18. The RAID system of claim 17, additionally comprising:

a bus, connecting array ASICs contained on each of the plurality of controller cards.

19. A single processor/single consumer queue, comprising:

memory, local to a processor, within which the queue is defined;

dispatcher code, resident in operating system code executed by the processor, to transfer information from the queue to the processor; and

an assist engine, to transfer work to the queue, the assist engine comprising;

mirrored memory, comprising a local mirrored memory block and a local array ASIC to maintain the local mirrored memory block; and

a coprocessor, configured to marshal and write information into the local mirrored memory block, and to read and de-marshal information from the mirrored memory block.

20. A processor-readable medium, comprising processor-executable instructions for transferring information between a first processor and a second processor, the processor-executable instructions comprising processor-executable instructions for:

in response to direction from the first processor, using a first coprocessor to write information in a first block of mirrored memory;

maintaining mirrored memory by associating an array ASIC with each block of mirrored memory and by providing communication between the array ASICs associated with each mirrored memory block;

reading, with a second coprocessor, the information from a second block of mirrored memory;

saving the information into a queue defined in memory local to the second processor; and

accessing the information with the second processor.

21. The processor readable media of claim 20, additionally comprising processor-executable instructions for marshalling the information with the first coprocessor.

22. The processor readable media of claim 21, additionally comprising processor-executable instructions for de-marshalling the information with the second coprocessor.

23. The processor readable media of claim 20, wherein accessing the information with a second processor comprises additional processor-executable instructions for using dispatcher code resident within operating system code executed by the second processor to access the information.

24. The processor readable media of claim 20, additionally comprising processor-executable instructions for:

configuring the second coprocessor to be a queue producer;

configuring the second processor to be a queue consumer; and

configuring the queue within memory managed by the operating system to which the coprocessor can write and the processor can read.

25. A system, comprising:

means for maintaining mirrored memory;

means for transferring information between coprocessors using mirrored memory, wherein the information is marshaled before being saved into a first section of mirrored memory by a first coprocessor and de-marshaled after being read from a second section of mirrored memory by a second coprocessor;

means for configuring processor/coprocessor pairs to support a single producer/single consumer queue, wherein the coprocessor is a producer and the processor is a consumer;

means for removing information from the single producer/single consumer queue; and

means for processing the information using software configured for operation on each processor.

26. The system of claim 25, additionally comprising:

means for reading the information by operating dispatcher code resident within operating system code configured for operation of the processor.

27. The system of claim 25, additionally comprising:

front code means for controlling the operation of input/output processors;

middle code means for controlling operation of a RAID device; and

back code means for controlling disk drive operation.

28. The system of claim 25, additionally comprising:

means for transferring information between coprocessors through the plurality of ASICs, not passing through mirrored memory.

29. A system, comprising:

a plurality of controller cards, each controller card comprising;

local memory;

a processor, in communication with the local memory; and

an assist engine, to transfer work to a queue, the assist engine comprising;

mirrored memory, comprising a local mirrored memory block; and

a coprocessor, configured to marshal and write information to the local mirrored memory block and to read and de-marshal information obtained from the local mirrored memory block.

30. The system of claim 29, additionally comprising:

a plurality of disks controlled by the plurality of controller cards.

31. The system of claim 29, wherein the assist engine additionally comprises:

a local array ASIC to maintain the local mirrored memory block with respect to mirrored memory blocks on other controller cards.