Intelligent data management fo hard disk drive

• US 20040015731A1
• Filed: 07/16/2002
• Published: 01/22/2004
• Est. Priority Date: 07/16/2002
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chu, Frank R., Hetzler, Steven R.
• Application Number:
  US10/195,478
• Publication Number:
  US 20040015731A1
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/3268 Power saving in hard disk drive
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G11B 19/02 Control of operating function, e.g. switching from recording to reproducing
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Power control logic in a disk drive controls a mode of operation of operational logic of the disk drive for reduced power consumption. The operational logic includes a first and a second mode of operation, such that the second mode of operation consumes less power than the first mode of operation. The power control logic includes a memory, and is coupled to communication signals over an interface. In response to a predetermined communication signal, the power control logic configures the memory for storing data that is related to the predetermined communication signal.

Claims

1. A device, comprising:

operational logic responsive to communication signals over an interface for performing input/output operations, the operational logic providing a first and a second mode of operation, the second mode of operation consuming less power than the first mode of operation; and

power control logic including a memory, the power control logic controlling the operational logic when the operational logic is in the second mode of operation, the power control logic being coupled to the communication signals over the interface and configuring the memory for storing data when a predetermined communication signal is received by the power control logic, the data being related to the predetermined signal.

2. The device according to claim 1, wherein the device is a disk drive.

3. The device according to claim 2, wherein the disk drive is connected to a host computer over the interface.

4. The device according to claim 2, wherein the disk drive is part of an electronic camera.

5. The device according to claim 2, wherein the disk drive is part of a personal digital music player.

6. The device according to claim 1, wherein the device is an optical drive.

7. The device according to claim 6, wherein the optical drive is connected to a host computer over the interface

8. The device according to claim 6, wherein the optical drive is part of an electronic camera.

9. The device according to claim 6, wherein the optical drive is part of a personal digital music player.

10. The device according to claim 6, wherein the device is one of a CD-ROM, a CD-RW, a CD-R, a DVD-ROM, a DVD-RW and a DVD-R.

11. The device according to claim 1, wherein the device is a network-attached storage device.

12. The device according to claim 11, wherein the network-attached storage device is connected to a host computer over the interface.

13. The device according to claim 1, wherein at least one of the operational logic and the power control logic is an electronic circuit.

14. The device according to claim 1, wherein the predetermined communication signal is a write data command, and

wherein the power control logic configures the memory to include a write cache, receives subsequently to the predetermined communication signal and stores the received write data in the write cache.

15. The device according to claim 14, wherein the power control logic controls the operational logic to transition to the first mode of operation and perform an output operation using the write data stored in the write cache when the memory is a predetermined percentage full containing the write data.

16. The device according to claim 15, wherein the predetermined percentage is based on a rate that write data is being stored in the write cache.

17. The device according to claim 1, wherein the predetermined communication signal is a read data command,

wherein the power control logic configures the memory to include a read cache and controls the operational logic in response to the predetermined communication signal to transition to the first mode of operation and perform an input operation, and

wherein the operational logic receives read data during the input operation and the power control logic stores the received read data in the read cache.

18. The device according to claim 17, wherein the read data is received during a read-ahead read operation.

19. The device according to claim 17, wherein the power control logic receives a second read command and performs an output operation when data corresponding to the second read command is stored in the read cache.

20. The device according to claim 1, wherein the memory includes a write cache and a read cache, and

wherein when the power control logic configures the memory for storing data, and enables at least one counter associated with one of the write cache and the read cache.

21. The device according to claim 1, wherein the power control logic is coupled to a bus circuit connected between the operational logic and a host computer.

22. The device according to claim 21, wherein the bus circuit is one of an ATA bus circuit, an SCSI bus circuit, a Serial ATA bus circuit, a Serial Attached SCSI bus circuit, a Fibre Channel bus circuit, a USB bus circuit, a Firewire bus circuit, a Gigabit Ethernet bus circuit, and an InfiBand bus circuit.

23. A method for controlling power of a device, the device having operational logic, the method comprising steps of:

detecting a communication signal over an interface intended for the operational logic of the device, the operational logic having a first mode of operation and a second mode of operation, the operational logic consuming more power in the first mode of operation than in the second mode of operation, the communication signal being detected when the operational logic is in the second mode of operation; and

configuring a memory for storing data when a predetermined communication signal is received by the power control logic, the data being related to the predetermined signal.

24. The method according to claim 23, wherein the device is a disk drive, an optical drive, or a network-attached storage device.

25. The method according to claim 24, wherein the device is connected to a host computer over the interface.

26. The method according to claim 24, wherein the device is part of an electronic camera.

27. The method according to claim 24, wherein the device is part of a personal digital music player.

28. The method according to claim 23, wherein the predetermined communication signal is a write data command, and

wherein the memory is configured to include a write cache,

the method further comprising steps of:

receiving write data received subsequent to the predetermined communication signal; and

storing the received write data in the write cache.

29. The method according to claim 28, further comprising steps of:

transitioning the operational logic to the first mode of operation; and

perform an output operation using the write data stored in the write cache when the memory is a predetermined percentage full containing the write data.

30. The method according to claim 29, wherein the predetermined percentage is based on a rate that write data is being stored in the write cache.

31. The method according to claim 23, wherein the predetermined communication signal is a read data command,

wherein the memory is configured to include a read cache,

the method further comprising steps of:

transitioning the operational logic to the first mode of operation in response to the predetermined communication signal;

performing an input operation receiving read data; and

storing the received read data in the read cache.

32. The method according to claim 31, further comprising a step of receiving the read data during a read-ahead read operation.

33. The method according to claim 31, further comprising steps of:

receiving a second read command; and

performing an output operation when data corresponding to the second read command is stored in the read cache.

34. The method according to claim 23, wherein the memory includes a write cache and a read cache, and

wherein the step of configuring the memory for storing data enables at least one counter associated with one of the write cache and the read cache.