Fault tolerant cell array architecture

• US 20040015735A1
• Filed: 02/19/2003
• Published: 01/22/2004
• Est. Priority Date: 03/22/1994
• Status: Active Grant

• Current Assignee: Richard S. Norman
• Original Assignee: 4536631 Canada Incorporated (Lowe's Cos., Inc.)
• Inventors: Norman, Richard S.
• Granted Patent: US 7,299,377 B2
• Time in Patent Office: Days
• US Class Current: 714/10
• CPC Class Codes: G02F 1/13318 Circuits comprising a photodetector
• CPC Class Codes: G02F 1/135 Liquid crystal cells structurally associated with a photoconducting or a ferro-electric layer, the properties of which can be optically or electrically varied G02F1/133348 takes precedence
• CPC Class Codes: G06F 11/2041 with more than one idle spare processing component
• CPC Class Codes: G06F 11/2051 in regular structures
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G06F 3/041 Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
• CPC Class Codes: G06F 3/043 using propagating acoustic waves
• CPC Class Codes: G06F 3/0488 using a touch-screen or digitiser, e.g. input of commands through traced gestures
• CPC Class Codes: G06F 3/04886 by partitioning the display area of the touch-screen or the surface of the digitising tablet into independently controllable areas, e.g. virtual keyboards or menus
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2330/08 Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/2085 Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
• CPC Class Codes: G09G 3/2088 with use of a plurality of processors, each processor controlling a number of individual elements of the matrix
• CPC Class Codes: H01L 27/1446 in a repetitive configuration
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14831 Area CCD imagers

Abstract

A data processing system containing a monolithic network of cells with sufficient redundancy provided through direct logical replacement of defective cells by spare cells to allow a large monolithic array of cells without uncorrectable defects to be organized, where the cells have a variety of useful properties. The data processing system according to the present invention overcomes the chip-size limit and off-chip connection bottlenecks of chip-based architectures, the von Neumann bottleneck of uniprocessor architectures, the memory and I/O bottlenecks of parallel processing architectures, and the input bandwidth bottleneck of high-resolution displays, and supports integration of up to an entire massively parallel data processing system into a single monolithic entity.

Claims

1. A fault tolerant data processing architecture comprising a monolithic network of cells having array cells and spare cells interconnected in such a manner that a plurality of spare cells can directly replace functions of any given array cell of the network should that given array cell prove defective without an overhead of a plurality of dedicated replacement cells for each array cell.

2. The architecture as claimed in claim 1 wherein the network of cells has sufficient redundancy that a fault-free array of cells can be organized.

3. The architecture as claimed in claim 1 wherein the network of cells has positional regularity.

4. The architecture as claimed in claim 1 further comprising means for directly addressing the cells of the fault-free array.

5. The architecture as claimed in claim 4 wherein means for directly addressing the cells comprises connecting the cells to a plurality address lines and disabling connections to unused lines.

6. The architecture as claimed in claim 1 wherein the cells of the fault-free array have positional regularity.

7. The architecture as claimed in claim 3 wherein the cells of the fault-free array have positional regularity.

8. The architecture as claimed in claim 1 further comprising means for higher than two-dimensional neighbor-to-neighbor communications between the cells of the fault-free array.

9. The architecture as claimed in claim 1 wherein the plurality of spare cells can directly replace a superset of functions of any given array cell.

10. The architecture as claimed in claim 1 further comprising means for self-testing.

11. The architecture as claimed in claim 10 means for self-testing further comprises means for array cells that test valid to vote to assassinate a defective neighbor cell by disconnecting a power supply of the defective neighbor cell.

12. A method for directly replacing defective array cells in a fault tolerant architecture, comprising steps of:

testing each array cell;

selecting a respective spare cell for each defective array cell; and

replacing the functions of the defective array cell with the respective spare cell.

13. The method as claimed in claim 12 wherein the step of testing each array cell comprises mapping a density of defective array cells surrounding each array cell.

14. The method as claimed in claim 13 wherein functions of defective cells are replaced in an order starting with a defective cell having a highest surrounding defect density and proceeding toward a defective cell having a lowest surrounding defect density.

15. The method as claimed in claim 12 wherein the step of testing each array cell comprises mapping a density of defective array cells surrounding each array cell.

16. The method as claimed in claim 15 wherein functions of defective cells are replaced in an order starting with a defective cell having a lowest number of unassigned spare cells and proceeding toward a defective cell having a highest number of unassigned spare cells.

17. A fault tolerant data processing architecture comprising:

a monolithic network of array memory cells and spare memory cells fabricated on a substrate that can be organized into a fault-free array of memory cells;

means for directly addressing each cell of the fault-free array of cells; and

means for each cell of the fault-free array of cells to send and receive data via a global data bus.

18. The architecture as claimed in claim 17 further comprising a processor fabricated on the substrate.

19. The architecture as claimed in claim 18 further comprising means for disabling the processor should the processor be found to be defective.

20. The architecture as claimed in claim 17 wherein the memory array further comprises a plurality of spare bit-lines for tolerating defective bits without requiring a spare cell.

21. The architecture as claimed in claim 17 wherein the memory array further comprises a plurality of spare word-lines for tolerating defective bits without requiring a spare cell.

22. The architecture as claimed in claim 17 further comprising functions selected from the group consisting of BIOS (basic input output system) chips, video accelerators and input/output controllers fabricated on the substrate.

23. A fault tolerant monolithic data processing architecture comprising:

a network of cells containing memory and processors that can be organized into a regular fault-free array of cells,

wherein the array of cells provides a parallel processing array.

24. The architecture as claimed in claim 23 further comprising:

means for the cells to communicate via a global bus; and

means for each cell to be directly addressed.

25. The architecture as claimed in claim 23 wherein the cells further comprise:

registers and local cache memory; and

means for using a register and/or a local cache memory of an array cell as a cache memory of a processor of another array cell.

26. The architecture as claimed in claim 23 wherein the cells contain dual-port memory.

27. A fault tolerant data processing architecture comprising:

a network of cells containing memory and processors that can be organized into a fault-free array;

means for communication between neighboring cells; and

means for input and output to a global data bus.

28. The architecture as claimed in claim 27 wherein means for communication between neighboring cells comprises direct connections.

29. The architecture as claimed in claim 27 wherein means for communication between neighboring cells comprises memory means placed between the neighboring cells and shared by the neighboring cells.

30. The architecture as claimed in claim 27 wherein means for communication between neighboring cells comprises alignment insensitive contacts.

31. The architecture as claimed in claim 27 further comprising a serial processor.

32. The architecture as claimed in claim 31 further comprising means for disabling the serial processor should the serial processor be found to be defective.

33. The architecture as claimed in claim 27 further comprising means for a spare cell replacing a defective cell to copy the defective cell'"'"'s memory whereby enabling dynamic recovery from a post-manufacturing defect is enabled.

34. A fault tolerant data processing architecture comprising a network of cells containing memory, processors and a direct output element that can be organized into a fault-free array, wherein the memory and processors are capable of extracting output data for the direct output from a compressed data stream.

35. A fault tolerant data processing architecture comprising a network of cells containing memory, processors that can be organized into a fault-free array, wherein each cell comprises:

a global input;

optical direct output means;

a count register;

a negative of a cell address; and

the processing power to add a number from the global input to the count register and check a result for a register overflow.

36. The architecture as claimed in claim 35 wherein a type of the direct optical output means is selected from a group consisting of light emitting diodes, liquid crystal display, semi-conductor lasers, ultra-miniature cathode ray tubes, field emitter displays and porous silicon.

37. In a fault tolerant data processing architecture a method for compressing and decompressing data for dynamic and static displays comprising steps of:

adding a number of cells controlled by an instruction to a counter register; and

determining a new value for a direct output means when the counter register overflows based on an opcode and a data portion of the instruction,

wherein the opcode portion of the instruction is chosen from a list comprising “

this cell'"'"'s output becomes”

(COB), “

next N cell'"'"'s output becomes the data portion”

(NCOB), “

next N cell'"'"'s output remains unchanged”

(NCRU), and “

reset”

(RES).

38. A fault tolerant data processing architecture comprising a network of cells containing memory, processors that can be organized into a fault-free array, wherein each cell comprises:

means for communicating with neighboring cells;

optical direct output means;

a count register;

a negative of a cell address; and

the processing power to add a number from the global input to the count register and check a result for a register overflow.

39. In a fault tolerant data processing architecture a method for compressing and decompressing data for dynamic and static displays comprising steps of:

passing a reset opcode from a current cell to a next cell in a data stream;

receiving a “

cell'"'"'s output becomes”

(COB) opcode with following data for an output value for output means of the current cell; and

removing the COB opcode and following data from the data stream;

receiving a “

next N cell'"'"'s output becomes”

(NCOB) opcode with following data for an output value for output means of next N cells;

decrementing a cell control counter;

if N is zero then the NCOB opcode and following data is removed from the data stream; and

receiving a “

next N cell'"'"'s output remains unchanged”

(NCRU);

decrementing the cell control counter;

if N is zero then the NCRU opcode and following data is removed from the data stream.

40. A fault tolerant data processing architecture comprising:

a monolithic network of cells having array cells and spare cells interconnected in such a manner that a plurality of spare cells can directly replace array cells; and

means to control display pixels of an array cell when replaced by a spare cell by disconnecting a power supply to the array cell.

41. A fault tolerant data processing architecture comprising:

a redundant monolithic network of cells that can be organized into a regular fault-free array of cells,

wherein each cell has direct output means, means for memory, means for processing and means for input.

42. The architecture as claimed in claim 41 wherein the direct output means is optical output means.

43. A fault tolerant data processing architecture comprising:

a redundant monolithic network of cells that can be organized into a regular fault-free array of cells,

wherein each cell has direct input means, direct output means, means for memory, means for processing and means for input.

44. The architecture as claimed in claim 43 wherein each cell further comprises access means to a global bus and means for communication with a neighboring cell.

45. The architecture as claimed in claim 43 wherein a type the direct input means is selected from the group consisting of optical, sonic, infra-red, and touch/proximity.

46. A fault tolerant data processing architecture comprising:

a redundant monolithic network of cells that can be organized into a regular fault-free array of cells,

wherein each cell has input and output means to a global data bus;

means for input and output communication with neighboring cells in a plurality of dimensions;

sufficient memory and processing power to decompress a data stream and to emulate at least one instruction from a microprocessor instruction set;

full color direct output means;

full color, capacitance touch/proximity direct input means; and

means to join a regional data bus.

47. A network of cells that can be organized into a fault-free array of cells, each one of said cells comprising direct input and/or output means;

means for memory;

means for processing; and

means for coordinating the phase and/or timing of the cell'"'"'s direct inputs and/or outputs with those of other cells.

48. The network of cells as claimed in claim 47, wherein each one of said cells further comprises input and output means to a global data bus.

49. A fault tolerant data processing architecture comprising:

a redundant monolithic network of cells that can be organized into a regular fault-free array of cells,

wherein each cell has input and output means to a global data bus;

direct input and/or output means;

means for memory;

means for processing; and

means for coordinating the phase and/or timing of the cell'"'"'s direct inputs and/or outputs with those of other cells.

50. A process for manufacturing a fault tolerant data processing architecture having a redundant monolithic network of cells that can be organized into a regular fault-free array of cells, comprising:

depositing a thin-film battery layer on a sheet of plastic;

depositing a first insulator layer;

depositing a power distribution layer;

depositing a second insulator layer;

etching a plurality of holes through the second insulator layer;

depositing conductors in the holes of the second insulator layer for providing access for cells to the power distribution layer;

depositing a processor/memory layer;

depositing a third insulator layer;

depositing a ground layer;

forming holes through to contacts in the processor memory layer;

depositing conductors in the holes of the third insulator layer for providing access for the processor/memory layer to a direct input/output layer;

depositing the direct input/output layer; and

depositing a protective layer.

52. A process for manufacturing as claimed in claim 50 wherein the step of depositing a processor/memory layer further comprises steps of:

depositing a layer of semiconductor material;

doping the layer of semiconductor material; and

connecting elements in the processor/memory layer.

51. A process for manufacturing a fault tolerant data processing architecture having a redundant monolithic network of cells that can be organized into a regular fault-free array of cells, comprising:

depositing, on a substrate or a sheet of plastic, a thin-film battery layer, a power distribution layer, a processor/memory layer, and a ground layer;

depositing an insulator layer between each one of said thin-film battery, power distribution, processor/memory, and ground layers;

providing holes with conductors for connecting cells to the power distribution layer;

providing holes with conductors for connecting the processor/memory layer to a direct input/output layer;

depositing the direct input/output layer; and

depositing a protective layer.