Fault tolerant cell array architecture
First Claim
1. A fault tolerant data processing architecture comprising a monolithic network of cells having array cells and spare cells interconnected in such a manner that a plurality of spare cells can directly replace functions of any given array cell of the network should that given array cell prove defective without an overhead of a plurality of dedicated replacement cells for each array cell.
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Accused Products
Abstract
A data processing system containing a monolithic network of cells with sufficient redundancy provided through direct logical replacement of defective cells by spare cells to allow a large monolithic array of cells without uncorrectable defects to be organized, where the cells have a variety of useful properties. The data processing system according to the present invention overcomes the chip-size limit and off-chip connection bottlenecks of chip-based architectures, the von Neumann bottleneck of uniprocessor architectures, the memory and I/O bottlenecks of parallel processing architectures, and the input bandwidth bottleneck of high-resolution displays, and supports integration of up to an entire massively parallel data processing system into a single monolithic entity.
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Citations
52 Claims
- 1. A fault tolerant data processing architecture comprising a monolithic network of cells having array cells and spare cells interconnected in such a manner that a plurality of spare cells can directly replace functions of any given array cell of the network should that given array cell prove defective without an overhead of a plurality of dedicated replacement cells for each array cell.
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12. A method for directly replacing defective array cells in a fault tolerant architecture, comprising steps of:
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testing each array cell;
selecting a respective spare cell for each defective array cell; and
replacing the functions of the defective array cell with the respective spare cell. - View Dependent Claims (13, 14, 15, 16)
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17. A fault tolerant data processing architecture comprising:
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a monolithic network of array memory cells and spare memory cells fabricated on a substrate that can be organized into a fault-free array of memory cells;
means for directly addressing each cell of the fault-free array of cells; and
means for each cell of the fault-free array of cells to send and receive data via a global data bus. - View Dependent Claims (18, 19, 20, 21, 22)
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23. A fault tolerant monolithic data processing architecture comprising:
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a network of cells containing memory and processors that can be organized into a regular fault-free array of cells, wherein the array of cells provides a parallel processing array. - View Dependent Claims (24, 25, 26)
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27. A fault tolerant data processing architecture comprising:
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a network of cells containing memory and processors that can be organized into a fault-free array;
means for communication between neighboring cells; and
means for input and output to a global data bus. - View Dependent Claims (28, 29, 30, 31, 32, 33)
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34. A fault tolerant data processing architecture comprising a network of cells containing memory, processors and a direct output element that can be organized into a fault-free array, wherein the memory and processors are capable of extracting output data for the direct output from a compressed data stream.
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35. A fault tolerant data processing architecture comprising a network of cells containing memory, processors that can be organized into a fault-free array, wherein each cell comprises:
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a global input;
optical direct output means;
a count register;
a negative of a cell address; and
the processing power to add a number from the global input to the count register and check a result for a register overflow. - View Dependent Claims (36)
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37. In a fault tolerant data processing architecture a method for compressing and decompressing data for dynamic and static displays comprising steps of:
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adding a number of cells controlled by an instruction to a counter register; and
determining a new value for a direct output means when the counter register overflows based on an opcode and a data portion of the instruction, wherein the opcode portion of the instruction is chosen from a list comprising “
this cell'"'"'s output becomes”
(COB), “
next N cell'"'"'s output becomes the data portion”
(NCOB), “
next N cell'"'"'s output remains unchanged”
(NCRU), and “
reset”
(RES).
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38. A fault tolerant data processing architecture comprising a network of cells containing memory, processors that can be organized into a fault-free array, wherein each cell comprises:
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means for communicating with neighboring cells;
optical direct output means;
a count register;
a negative of a cell address; and
the processing power to add a number from the global input to the count register and check a result for a register overflow.
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39. In a fault tolerant data processing architecture a method for compressing and decompressing data for dynamic and static displays comprising steps of:
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passing a reset opcode from a current cell to a next cell in a data stream;
receiving a “
cell'"'"'s output becomes”
(COB) opcode with following data for an output value for output means of the current cell; and
removing the COB opcode and following data from the data stream;
receiving a “
next N cell'"'"'s output becomes”
(NCOB) opcode with following data for an output value for output means of next N cells;
decrementing a cell control counter;
if N is zero then the NCOB opcode and following data is removed from the data stream; and
receiving a “
next N cell'"'"'s output remains unchanged”
(NCRU);
decrementing the cell control counter;
if N is zero then the NCRU opcode and following data is removed from the data stream.
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40. A fault tolerant data processing architecture comprising:
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a monolithic network of cells having array cells and spare cells interconnected in such a manner that a plurality of spare cells can directly replace array cells; and
means to control display pixels of an array cell when replaced by a spare cell by disconnecting a power supply to the array cell.
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41. A fault tolerant data processing architecture comprising:
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a redundant monolithic network of cells that can be organized into a regular fault-free array of cells, wherein each cell has direct output means, means for memory, means for processing and means for input. - View Dependent Claims (42)
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43. A fault tolerant data processing architecture comprising:
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a redundant monolithic network of cells that can be organized into a regular fault-free array of cells, wherein each cell has direct input means, direct output means, means for memory, means for processing and means for input. - View Dependent Claims (44, 45)
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46. A fault tolerant data processing architecture comprising:
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a redundant monolithic network of cells that can be organized into a regular fault-free array of cells, wherein each cell has input and output means to a global data bus;
means for input and output communication with neighboring cells in a plurality of dimensions;
sufficient memory and processing power to decompress a data stream and to emulate at least one instruction from a microprocessor instruction set;
full color direct output means;
full color, capacitance touch/proximity direct input means; and
means to join a regional data bus.
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47. A network of cells that can be organized into a fault-free array of cells, each one of said cells comprising direct input and/or output means;
means for memory;
means for processing; and
means for coordinating the phase and/or timing of the cell'"'"'s direct inputs and/or outputs with those of other cells.- View Dependent Claims (48)
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49. A fault tolerant data processing architecture comprising:
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a redundant monolithic network of cells that can be organized into a regular fault-free array of cells, wherein each cell has input and output means to a global data bus;
direct input and/or output means;
means for memory;
means for processing; and
means for coordinating the phase and/or timing of the cell'"'"'s direct inputs and/or outputs with those of other cells.
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50. A process for manufacturing a fault tolerant data processing architecture having a redundant monolithic network of cells that can be organized into a regular fault-free array of cells, comprising:
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depositing a thin-film battery layer on a sheet of plastic;
depositing a first insulator layer;
depositing a power distribution layer;
depositing a second insulator layer;
etching a plurality of holes through the second insulator layer;
depositing conductors in the holes of the second insulator layer for providing access for cells to the power distribution layer;
depositing a processor/memory layer;
depositing a third insulator layer;
depositing a ground layer;
forming holes through to contacts in the processor memory layer;
depositing conductors in the holes of the third insulator layer for providing access for the processor/memory layer to a direct input/output layer;
depositing the direct input/output layer; and
depositing a protective layer. - View Dependent Claims (52)
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51. A process for manufacturing a fault tolerant data processing architecture having a redundant monolithic network of cells that can be organized into a regular fault-free array of cells, comprising:
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depositing, on a substrate or a sheet of plastic, a thin-film battery layer, a power distribution layer, a processor/memory layer, and a ground layer;
depositing an insulator layer between each one of said thin-film battery, power distribution, processor/memory, and ground layers;
providing holes with conductors for connecting cells to the power distribution layer;
providing holes with conductors for connecting the processor/memory layer to a direct input/output layer;
depositing the direct input/output layer; and
depositing a protective layer.
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Specification