System and method for preventing software errors

• US 20040015747A1
• Filed: 07/18/2002
• Published: 01/22/2004
• Est. Priority Date: 07/18/2002
• Status: Active Grant

• Current Assignee: Valtrus Innovations Limited (f/k/a Dolya Holdco 9 Limited) (Key Patent Innovations Limited)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Dwyer, Lawrence D.K.B.
• Granted Patent: US 6,990,612 B2
• Time in Patent Office: Days
• US Class Current: 714/47
• CPC Class Codes: G06F 11/3644 by instrumenting at runtime
• CPC Class Codes: G06F 8/54 Link editing before load time

Abstract

The present invention provides systems and methods for preventing software errors caused by address range or alignment errors. In architecture, a representative system includes a compiler that parses a program and further comprises a logic that generates a verification value for a block of code in the program, a logic that stores the verification value in the block of code, and a logic that inserts verification value instruction code into the block of code. The present invention can also be viewed as a method for preventing software errors in a program. A representative method operates by generating a verification value for a block of code in the program, and storing the verification value in the block of code. During execution of the program, a runtime verification value is generated for the block of code, and the block of code is executed if the verification value equals the runtime verification value, and generates an error message if the verification value does not equals the runtime verification value.

Claims

1. A method for preventing software errors in a program, said method comprising steps of:

generating a verification value for a block of code in the program;

storing the verification value in the block of code;

computing a runtime verification value for the block of code during execution of the program;

executing the block of code if the verification value equals the runtime verification value; and

generating an error message if the verification value does not equal the runtime verification value.

2. The method of claim 1, wherein the generating a verification value step further comprises:

allocating area for the generated verification value.

3. The method of claim 1, wherein the generating a verification value step further comprises:

inserting the verification value in the block of code.

4. The method of claim 1, further comprising the step of:

inserting verification value instruction code into the block of code.

5. The method of claim 1, wherein the generating a verification value step further comprises:

using a parameter to generate the verification value, wherein the parameter is selected from the group consisting of a base address of the block of code, number of elements in the block of code, type of the elements in the block of code, and order of the elements in the block of code.

6. The method of claim 1, wherein the verification value is a hash value.

7. A system for preventing software errors in a program, comprising:

means for generating a verification value for a block of code in the program;

means for storing the verification value in the block of code; and

means for computing a runtime verification value for the block of code during execution of the program, wherein the computing means executes the block of code if the verification value equals the runtime verification value, and generates an error message if the verification value does not equal the runtime verification value.

8. The system of claim 7, wherein the generating means further comprises:

means for allocating area for the generated verification value.

9. The system of claim 7, wherein the generating means further comprises:

means for inserting the verification value in the block of code.

10. The system of claim 7, wherein the generating means further comprises:

means for inserting verification value instruction code into the block of code.

11. The system of claim 7, wherein the verification value is generated using a parameter, wherein the parameter is selected from the group consisting of a base address of the block of code, number of elements in the block of code, type of the elements in the block of code, and order of the elements in the block of code.

12. The system of claim 7, wherein the verification value is a hash value.

13. A computer readable medium for preventing software errors in a program, comprising:

logic for generating a verification value for a block of code in the program;

logic for storing the verification value in the block of code; and

logic for computing a runtime verification value for the block of code during execution of the program, wherein the computing logic executes the block of code if the verification value equals the runtime verification value, and generates an error message if the verification value does not equal the runtime verification value.

14. The computer readable medium of claim 13, wherein said logic for generating a verification value further comprises:

logic for allocating area for the verification value.

15. The computer readable medium of claim 13, wherein said logic for generating a verification value further comprises:

logic for inserting the verification value in the block of code.

16. The computer readable medium of claim 13, wherein said logic for generating a verification value further comprises:

logic for inserting verification value instruction code into the block of code.

17. The computer readable medium of claim 13, wherein the verification value is generated using a parameter, wherein the parameter is selected from the group consisting of a base address of the block of code, number of elements in the block of code, type of the elements in the block of code, and order of the elements in the block of code.

18. The computer readable medium of claim 13, wherein the verification value is a hash value.

19. A system for preventing software errors in a program, comprising:

a compiler that parses a program, wherein the compiler further comprises;

logic that generates a verification value for a block of code in the program;

logic that stores the verification value in the block of code; and

logic that inserts verification value instruction code into the block of code.

20. The system of claim 19, wherein the compiler further comprises:

logic that allocates area in the block of code for the verification value.

21. The system of claim 19, wherein the compiler further comprises:

logic that for inserts the verification value in the block of code.

22. The system of claim 19, wherein the verification value is generated using

a parameter, wherein the parameter is selected from the group consisting of a base address of the block of code, number of elements in the block of code, type of the elements in the block of code, and order of the elements in the block of code.

23. The system of claim 19, wherein the verification value is a hash value.