Updating high speed parallel I/O interfaces based on counters
First Claim
1. A communication system, comprising:
- a first link, wherein the first link comprises a first data line arranged to transmit a first data signal and a first clock line arranged to transmit a first clock signal;
a first latch device arranged to latch the first data signal; and
a first test circuit operatively connected to the first link, wherein the first test circuit is arranged to test the first link, the first test circuit comprising;
a first adjustment circuit arranged to generate a first adjustable clock signal based on the first clock signal, wherein the first adjustment circuit is arranged to adjust a timing of the first adjustable clock signal relative to the first data signal when the first link is tested, and wherein the first latch device is responsive to the first adjustable clock signal, and a first pattern comparator arranged to compare a first latched test pattern signal to a first test pattern signal, wherein the first latch device is arranged to latch the first test pattern signal from the first data line to generate the first latched test pattern signal; and
a counter, wherein the first test circuit is arranged to test the first link based on the counter.
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Accused Products
Abstract
A technique for adjusting a communication system involves a link, where the link includes a data line arranged to transmit a data signal and a clock line adapted to transmit a clock signal. The technique uses one or more counters to test the transmission across the link. Dependent on one or more of these counters, a test circuit, connected to the link, compares a known test pattern signal to a latched test pattern signal transmitted on the data line. The test circuit includes an adjustment circuit arranged to generate an adjustable clock signal from the clock signal, where the adjustable clock signal determines when to latch the transmitted test pattern signal The test circuit adjusts a timing of the adjustable clock signal relative to the data signal of the link.
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Citations
20 Claims
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1. A communication system, comprising:
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a first link, wherein the first link comprises a first data line arranged to transmit a first data signal and a first clock line arranged to transmit a first clock signal;
a first latch device arranged to latch the first data signal; and
a first test circuit operatively connected to the first link, wherein the first test circuit is arranged to test the first link, the first test circuit comprising;
a first adjustment circuit arranged to generate a first adjustable clock signal based on the first clock signal, wherein the first adjustment circuit is arranged to adjust a timing of the first adjustable clock signal relative to the first data signal when the first link is tested, and wherein the first latch device is responsive to the first adjustable clock signal, and a first pattern comparator arranged to compare a first latched test pattern signal to a first test pattern signal, wherein the first latch device is arranged to latch the first test pattern signal from the first data line to generate the first latched test pattern signal; and
a counter, wherein the first test circuit is arranged to test the first link based on the counter. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A communication system updating method, comprising:
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testing a first adjustable clock signal for a first link, comprising;
transmitting a first test pattern signal on a first data line of the first link, latching the first test pattern signal based on the first adjustable clock signal to generate a first latched test pattern signal, comparing the first latched test pattern signal to the first test pattern signal, and adjusting a first offset of the first adjustable clock signal based on the comparing the first latched test pattern signal; and
determining when the testing the first adjustable clock signal occurs based on a counter. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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20. A communication system, comprising:
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means for testing an adjustable clock signal for a link, comprising;
means for transmitting a test pattern signal on a data line of the link, means for latching the test pattern signal based on the adjustable clock signal to generate a latched test pattern signal, means for comparing the latched test pattern signal to the test pattern signal, and means for adjusting an offset of the adjustable clock based on the means for comparing; and
means for determining when the means for testing occurs.
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Specification