Updating high speed parallel I/O interfaces based on counters

• US 20040015751A1
• Filed: 07/16/2002
• Published: 01/22/2004
• Est. Priority Date: 07/16/2002
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Liu, Dean, Amick, Brian W., Roy, Aninda K., Gauthier, Claude R.
• Granted Patent: US 7,062,688 B2
• Time in Patent Office: Days
• US Class Current: 714/712
• CPC Class Codes: G06F 11/24 Marginal checking or other specified testing methods not covered by G06F11/26, e.g. race tests

Abstract

A technique for adjusting a communication system involves a link, where the link includes a data line arranged to transmit a data signal and a clock line adapted to transmit a clock signal. The technique uses one or more counters to test the transmission across the link. Dependent on one or more of these counters, a test circuit, connected to the link, compares a known test pattern signal to a latched test pattern signal transmitted on the data line. The test circuit includes an adjustment circuit arranged to generate an adjustable clock signal from the clock signal, where the adjustable clock signal determines when to latch the transmitted test pattern signal The test circuit adjusts a timing of the adjustable clock signal relative to the data signal of the link.

Claims

1. A communication system, comprising:

a first link, wherein the first link comprises a first data line arranged to transmit a first data signal and a first clock line arranged to transmit a first clock signal;

a first latch device arranged to latch the first data signal; and

a first test circuit operatively connected to the first link, wherein the first test circuit is arranged to test the first link, the first test circuit comprising;

a first adjustment circuit arranged to generate a first adjustable clock signal based on the first clock signal, wherein the first adjustment circuit is arranged to adjust a timing of the first adjustable clock signal relative to the first data signal when the first link is tested, and wherein the first latch device is responsive to the first adjustable clock signal, and

a first pattern comparator arranged to compare a first latched test pattern signal to a first test pattern signal, wherein the first latch device is arranged to latch the first test pattern signal from the first data line to generate the first latched test pattern signal; and

a counter, wherein the first test circuit is arranged to test the first link based on the counter.

2. The communication system of claim 1, further comprising:

a second link, wherein the second link comprises a second data line arranged to transmit a second data signal and a second clock line arranged to transmit a second clock signal;

a second latch device arranged to latch the second data signal; and

a second test circuit operatively connected to the second link, wherein the second test circuit is arranged to test the second link, the second test circuit comprising;

a second adjustment circuit arranged to generate a second adjustable clock signal based on the second clock signal, wherein the second adjustment circuit is arranged to adjust a timing of the second adjustable clock signal relative to the second data signal when the second link is tested, and wherein the second latch device is responsive to the second adjustable clock signal, and

a second pattern comparator arranged to compare a second latched test pattern signal to a second test pattern signal, wherein the second latch device is arranged to latch the second test pattern signal from the second data line to generate the second latched test pattern signal; and

wherein the second test circuit is arranged to test the second link based on the counter.

3. The communication system of claim 1, further comprising:

a processor, responsive to the counter, arranged to initiate a test of the first link.

4. The communication system of claim 3, wherein the processor is arranged to cause the first test pattern signal to be transmitted on the first link.

5. The communication system of claim 1, wherein the first test circuit is arranged to cause the first test pattern signal to be transmitted on the first link.

6. The communication system of claim 1, wherein the counter is arranged to set a minimum duration between the first test circuit testing the first link a first time and a second time.

7. The communication system of claim 1, wherein the counter counts one selected from the group consisting of clock cycles, instructions, and a quantity of received data.

8. The communication system of claim 1, wherein the counter counts a time interval.

9. The communication system of claim 1, wherein the first test circuit is arranged to test the first link periodically.

10. The communication system of claim 1, wherein the first adjustable clock signal is generated from one selected from the group consisting of a voltage controlled delay line, a digital delay line, and an analog delay line.

11. A communication system updating method, comprising:

testing a first adjustable clock signal for a first link, comprising;

transmitting a first test pattern signal on a first data line of the first link,

latching the first test pattern signal based on the first adjustable clock signal to generate a first latched test pattern signal,

comparing the first latched test pattern signal to the first test pattern signal, and

adjusting a first offset of the first adjustable clock signal based on the comparing the first latched test pattern signal; and

determining when the testing the first adjustable clock signal occurs based on a counter.

12. The method of claim 11, further comprising:

testing a second adjustable clock signal for a second link, comprising;

transmitting a second test pattern signal on a second data line of the second link,

latching the second test pattern signal based on the second adjustable clock signal to generate a second latched test pattern signal,

comparing the second latched test pattern signal to the second test pattern signal, and

adjusting a second offset of the second adjustable clock signal based on the comparing the second latched test pattern signal; and

wherein the testing the second adjustable clock signal occurs based on the counter.

13. The method of claim 11, further comprising:

using a processor to initiate the testing of the first adjustable clock signal.

14. The method of claim 13, wherein the transmitting the first test pattern signal is initiated by the processor.

15. The method of claim 11, wherein the counter determines a minimum duration between the testing a first adjustable clock signal a first time and a second time.

16. The method of claim 11, wherein the counter counts one selected from the group consisting of clock cycles, instructions, and a quantity of received data.

17. The method of claim 11, wherein the counter counts a time interval.

18. The method of claim 11, wherein the testing the first adjustable clock signal occurs periodically.

19. The method of claim 11, wherein the adjusting the first offset uses at least one selected from the group consisting of a voltage-controlled delay line, a digital delay line, and an analog delay line.

20. A communication system, comprising:

means for testing an adjustable clock signal for a link, comprising;

means for transmitting a test pattern signal on a data line of the link,

means for latching the test pattern signal based on the adjustable clock signal to generate a latched test pattern signal,

means for comparing the latched test pattern signal to the test pattern signal, and

means for adjusting an offset of the adjustable clock based on the means for comparing; and

means for determining when the means for testing occurs.