Methodology for the optimization of testing and diagnosis of analog and mixed signal ICs and embedded cores

• US 20040015793A1
• Filed: 01/09/2003
• Published: 01/22/2004
• Est. Priority Date: 01/10/2002
• Status: Active Grant

• Current Assignee: PDF Solutions
• Original Assignee: PDF Solutions
• Inventors: Saxena, Sharad, Daldoss, Lidia, Guardiani, Carlo, McNamara, Patrick D.
• Granted Patent: US 7,003,742 B2
• Time in Patent Office: Days
• US Class Current: 716/4
• CPC Class Codes: G01R 31/3167 Testing of combined analog and digital circuits testing ADC's H03M1/1071
• CPC Class Codes: G01R 31/318357 Simulation computer simulation of digital circuits G06F30/3308
• CPC Class Codes: G01R 31/318364 as a result of hardware simulation, e.g. in an HDL environment computer-aided simulation of circuits G06F30/3308
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A method for analyzing an integrated circuit (IC) having at least one of the group consisting of digital and analog components, where the IC is designed to meet a plurality of circuit performance specifications, and fabrication of the IC is monitored by measuring process factors and a previously defined set of electrical test variables. A set of linearly independent electrical test parameters are formed based on a subset of the set of electrical test variables. The set of process factors is mapped to the linearly independent electrical test parameters. A plurality of figure-of-merit (FOM) performance models are formed based on the process factors. The FOM models are combined with the mapping to enable modeling of IC performance based on the linearly independent electrical test parameters.

Claims

1. A method for analyzing an integrated circuit (IC) having at least one of the group consisting of digital and analog components, wherein the IC is designed to meet a plurality of circuit performance specifications, and fabrication of the IC is monitored by measuring process factors and a previously defined set of electrical test variables, the method comprising the steps of:

(a) forming a set of linearly independent electrical test parameters based on a subset of the set of electrical test variables;

(b) mapping the set of process factors to the linearly independent electrical test parameters;

(c) forming a plurality of figure-of-merit (FOM) performance models based on the process factors; and

(d) combining the FOM models with the mapping to enable modeling of IC performance based on the linearly independent electrical test parameters.

2. The method of claim 1, wherein step (a) includes:

(i) detecting at least two of the set of electrical test variables that provide redundant information;

(ii) forming a subset of the set of electrical test variables, excluding from the subset at least one of the detected variables;

(iii) transforming the subset of electrical tests to the set of linearly independent principle components.

3. The method of claim 2, wherein the detecting step includes detecting at least two of the set of electrical test variables that are highly correlated with each other.

4. The method of claim 2, wherein step (iii) includes performing a principle component transformation.

5. The method of claim 4, wherein the principle component transformation includes at least one of the group consisting of QR decomposition, singular value decomposition and LU factorization.

6. The method of claim 1, wherein the FOM models are response surface methodology models.

7. The method of claim 1, wherein the FOM models include at least one of the group consisting of quadratic performance models and linear performance models.

8. The method of claim 1, further comprising:

selecting a plurality of different designs of experiment (DOE) based on respective combinations of the process factors;

generating a respective response FOM model for each DOE; and

analyzing sensitivity of circuit performance to each of the process factors.

9. The method of claim 8, further comprising:

adding at least one additional electrical test to the set of electrical test variables, based on the sensitivity analysis.

10. The method of claim 9, further comprising repeating steps (a) through (d)

11. A method for analyzing an integrated circuit (IC) having digital and analog components, wherein the IC is designed to meet a plurality of circuit performance specifications, and fabrication of the IC is monitored by measuring process factors and a previously defined set of electrical test variables, the method comprising the steps of:

(a) detecting at least two of the set of electrical test variables that that are highly correlated with each other;

(b) forming a subset of the set of electrical test variables, excluding from the subset at least one of the detected variables;

(c) transforming the subset of electrical tests by a principle component transformation to a set of linearly independent principle components;

(d) mapping the set of process factors to the linearly independent electrical test parameters;

(e) forming a plurality of figure-of-merit (FOM) performance response surface methodology models based on the process factors; and

(f) combining the FOM models with the mapping to enable modeling of IC performance based on the linearly independent electrical test parameters.

12. The method of claim 11, further comprising:

selecting a plurality of different designs of experiment (DOE) based on respective combinations of the process factors;

generating a respective response FOM model for each DOE; and

analyzing sensitivity of circuit performance to each of the process factors.

13. The method of claim 12, further comprising:

adding at least one additional electrical test to the set of electrical test variables, based on the sensitivity analysis.

14. The method of claim 13, further comprising repeating steps (a) through (d)