Verifying proximity of ground vias to signal vias in an integrated circuit

• US 20040015796A1
• Filed: 07/19/2002
• Published: 01/22/2004
• Est. Priority Date: 07/19/2002
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Moldauer, Peter Shaw, Frank, Mark D., Nelson, Jerimy
• Granted Patent: US 6,922,822 B2
• Time in Patent Office: Days
• US Class Current: 716/5
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Techniques are disclosed for verifying the proximity of ground vias to signal vias in an integrated circuit package design. A package designer creates the package design using a package design tool. A proximity verifier verifies that there is a ground via within a predetermined threshold distance of each specified signal via in the package design. The proximity verifier may notify the package designer of any signal vias which are not sufficiently close to ground vias, such as by providing visual indications of such signal vias in a graphical representation of the package design displayed on a display monitor. In response, the package designer may modify the package model to ensure that all signal vias are sufficiently close to ground vias. The proximity verifier may be implemented as a design rule which may be executed automatically and in real-time by the package design tool.

Claims

1. A computer-implemented method comprising steps of:

(A) identifying a signal via in an integrated, circuit design; and

(B) determining whether there is at least one signal return path in the integrated circuit design within a predetermined threshold distance from the signal via.

2. The method of claim 1, wherein the step (A) comprises a step of identifying coordinates of the signal via, and wherein the step (B) comprises steps of:

(B)(1) identifying coordinates of a first signal return path in the integrated circuit design; and

(B)(2) determining whether the signal via coordinates differ from the first signal return path coordinates by more than the predetermined threshold distance.

3. The method of claim 2, wherein the step (B)(1) comprises a step of identifying a plurality of coordinates of the first signal return path, and wherein the step (B)(2) comprises steps of:

(B)(2)(a) determining whether the signal via coordinates differ from any of the plurality of signal return path coordinates by more than the predetermined threshold distance;

(B)(2)(b) determining that there is no signal return path within the predetermined threshold distance of the signal via if it is determined in step (B)(2)(a) that the signal via coordinates differ from any of the signal return path coordinates by more than the predetermined threshold distance; and

(B)(2)(c) determining that there is a signal return path within the predetermined threshold distance of the signal via if it is determined in step (B)(2)(a) that the segment coordinates differ from none of the signal return path coordinates by more than the predetermined threshold distance.

4. The method of claim 2, wherein the signal via coordinates comprise two-dimensional coordinates within a first layer of the integrated circuit design, wherein the first signal return path coordinates comprise two-dimensional coordinates within the first layer of the integrated circuit design, and wherein the step (B)(2) comprises steps of:

(B)(2)(a) identifying the length of a line having as endpoints the signal via coordinates and the first signal return path coordinates;

(B)(2)(b) determining that the signal via coordinates differ from the first signal return path coordinates by more than the predetermined threshold distance if the length of the identified line is greater than the predetermined threshold distance; and

(B)(2)(c) determining that the signal coordinates do not differ from the first signal return path coordinates by more than the predetermined threshold distance if the length of the identified line is not greater than the predetermined threshold distance.

5. The method of claim 2, wherein the signal via coordinates comprise coordinates of the center of a cross-section of the signal via within a first layer of the integrated circuit design.

6. The method of claim 2, wherein the signal via coordinates comprise coordinates of an edge of a cross-section of the signal via within a first layer of the integrated circuit design.

7. The method of claim 3, wherein the first signal return path comprises all signal return paths in the integrated circuit design.

8. The method of claim 1, wherein the signal via comprises one of a plurality of signal vias in the integrated circuit design, and wherein the method further comprises a step of:

(C) performing the steps (A) and (B) for each of the plurality of signal vias.

9. The method of claim 1, wherein the integrated circuit design comprises a computer-implemented model of an integrated circuit tangibly stored in a computer-readable medium.

10. The method of claim 1, further comprising a step of:

(C) providing an error indication if it is determined in the step (B) that there is no signal return path in the integrated circuit design within the predetermined threshold distance from the signal via.

11. The method of claim 10, wherein the indication comprises a visual indication in a graphical representation of the integrated circuit design.

12. The method of claim 1, wherein the signal return path comprises ground metal.

13. The method of claim 1, wherein the signal return path comprises power.

14. The method of claim 1, wherein the step (A) comprises a step of identifying a plurality of layers in the integrated circuit design containing the signal via, and wherein the step (B) comprises a step of determining whether there is at least one signal return path in each of the plurality of layers within the predetermined threshold distance from the signal via.

15. A system comprising:

a computer-readable medium tangibly embodying an integrated circuit design; and

signal via identification means for identifying a signal via in the integrated circuit design; and

first proximity verification means for determining whether there is a signal return path in the integrated circuit design within a predetermined threshold distance from the signal via.

16. The system of claim 15, wherein the signal via identification means comprises means for identifying coordinates of the signal via, and wherein the first proximity verification means comprises:

first signal return path coordinate identification means for identifying coordinates of a first signal return path in the integrated circuit design; and

first coordinate comparison means for determining whether the signal via coordinates differ from the first signal return path coordinates by more than the predetermined threshold distance.

17. The system of claim 16, wherein the first signal return path coordinate identification means comprises means for identifying a plurality of coordinates of the first signal return path in the integrated circuit design, and wherein the first coordinate comparison means comprises:

means for determining whether the signal via coordinates differ from any of the plurality of signal return path coordinates by more than the predetermined threshold distance;

means for determining that there is no signal return path within the predetermined threshold distance of the signal via if it is determined that the signal via coordinates differ from any of the signal return path coordinates by more than the predetermined threshold distance; and

means for determining that there is a signal return path within the predetermined threshold distance of the signal trace segment if it is determined that the signal via coordinates differ from none of the signal return path coordinates by more than the predetermined threshold distance.

18. The system of claim 16, wherein the signal via coordinates comprise two-dimensional coordinates within the first layer of the integrated circuit design, wherein the first signal return path coordinates comprise two-dimensional coordinates within the second layer of the integrated circuit design, and wherein the first coordinate comparison means comprises:

means for identifying the length of a line having as endpoints the signal via coordinates and the first signal return path coordinates;

means for determining that the signal via coordinates differ from the first signal return path coordinates by more than the predetermined threshold distance if the length of the identified line is greater than the predetermined threshold distance; and

means for determining that the signal via coordinates do not differ from the first signal return path coordinates by more than the predetermined threshold distance if the length of the identified line is not greater than the predetermined threshold distance.

19. The system of claim 16, wherein the signal via coordinates comprise coordinates of the center of a cross-section of the signal via within a first layer of the integrated circuit design.

20. The system of claim 16, wherein the signal via coordinates comprise coordinates of an edge of a cross-section of the signal via within a first layer of the integrated circuit design.

21. The system of claim 17, wherein the first signal return path comprises all signal return paths in the integrated circuit design.

22. The system of claim 15, wherein the signal via comprises one of a plurality of signal vias in the integrated circuit design, and wherein the system further comprises:

segment iteration means for applying the signal via identification means and the first proximity verification means to each of the plurality of signal vias.

23. The system of claim 15, wherein the integrated circuit design comprises a computer-implemented model of an integrated circuit tangibly stored in a computer-readable medium.

24. The system of claim 15, further comprising:

means for providing an error indication if it is determined that there is no signal return path in the integrated circuit design within the predetermined threshold distance from the signal via.

25. The system of claim 24, wherein the indication comprises a visual indication in a graphical representation of the integrated circuit design.

26. The system of claim 15, wherein the signal via identification means and the first proximity verification means comprise a computer program written in the Skill scripting language.

27. The system of claim 15, wherein the signal via identification means and the first proximity verification means comprise a design rule tangibly embodied in the computer-readable medium, wherein the design rule is defined according to a specification associated with an electronic design automation tool.

28. The system of claim 27, wherein the integrated circuit design includes the design rule.

29. The system of claim 15, wherein the signal return path comprises ground metal.

30. The system of claim 15, wherein the signal return path comprises power.