Layout quality analyzer
First Claim
1. A method comprising:
- computing a first plurality of routes, each route of the first plurality of routes corresponding to a respective net of a plurality of nets in an integrated circuit layout, and each route representing a theoretically optimal route of the respective net according to a graph theory based algorithm; and
comparing each of the first plurality of routes to a corresponding route of a current plurality of routes, each of the current plurality of routes corresponding to the respective net of the plurality of nets and currently existing in the integrated circuit layout.
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Abstract
In one embodiment, a computer readable medium comprises at least first instructions and second instructions. The first instructions, when executed, compute a first plurality of routes. Each route of the first plurality of routes corresponds to a respective net of a plurality of nets in an integrated circuit layout, and represents a theoretically optimal route of the respective net according to a graph theory based algorithm. The second instructions, when executed, compare each of the first plurality of routes to a corresponding route of a current plurality of routes, each of the current plurality of routes corresponding to the respective net of the plurality of nets and currently existing in the integrated circuit layout. A method is also contemplated.
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Citations
34 Claims
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1. A method comprising:
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computing a first plurality of routes, each route of the first plurality of routes corresponding to a respective net of a plurality of nets in an integrated circuit layout, and each route representing a theoretically optimal route of the respective net according to a graph theory based algorithm; and
comparing each of the first plurality of routes to a corresponding route of a current plurality of routes, each of the current plurality of routes corresponding to the respective net of the plurality of nets and currently existing in the integrated circuit layout. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 34)
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18. A computer readable medium comprising:
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first instructions which, when executed, compute a first plurality of routes, each route of the first plurality of routes corresponding to a respective net of a plurality of nets in an integrated circuit layout, and each route representing a theoretically optimal route of the respective net according to a graph theory based algorithm; and
second instructions which, when executed, compare each of the first plurality of routes to a corresponding route of a current plurality of routes, each of the current plurality of routes corresponding to the respective net of the plurality of nets and currently existing in the integrated circuit layout. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33)
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Specification