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Layout quality analyzer

  • US 20040015805A1
  • Filed: 07/22/2002
  • Published: 01/22/2004
  • Est. Priority Date: 07/22/2002
  • Status: Active Grant
First Claim
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1. A method comprising:

  • computing a first plurality of routes, each route of the first plurality of routes corresponding to a respective net of a plurality of nets in an integrated circuit layout, and each route representing a theoretically optimal route of the respective net according to a graph theory based algorithm; and

    comparing each of the first plurality of routes to a corresponding route of a current plurality of routes, each of the current plurality of routes corresponding to the respective net of the plurality of nets and currently existing in the integrated circuit layout.

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