Silicon nitride antifuse for use in diode-antifuse memory arrays

• US 20040016991A1
• Filed: 06/30/2003
• Published: 01/29/2004
• Est. Priority Date: 04/28/2000
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Herner, S. Brad, Johnson, Mark G., Knall, N. Johan
• Granted Patent: US 8,575,719 B2
• Time in Patent Office: Days
• US Class Current: 257/530
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H01L 21/822 the substrate being a semiconductor, using silicon technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence

Abstract

Silicon nitride antifuses can be advantageously used in memory arrays employing diode-antifuse cells. Silicon nitride antifuses can be ruptured faster and at a lower breakdown field than antifuses formed of other materials, such as silicon dioxide. Examples are given of monolithic three dimensional memory arrays using silicon nitride antifuses with memory cells disposed in rail-stacks and pillars, and including PN and Schottky diodes. Pairing a silicon nitride antifuse with a low-density, high-resistivity conductor gives even better device performance.

Claims

1. A memory array comprising a plurality of memory cells, each memory cell comprising:

a first diode portion;

a second diode portion vertically above the first diode portion; and

a silicon nitride antifuse in contact with the first or the second diode portion.

2. The memory array of claim 1, wherein the antifuse is vertically above the second diode portion.

3. The memory array of claim 2, wherein

the first diode portion comprises semiconductor material of a first conductivity type, and

the second diode portion comprises semiconductor material of a second conductivity type opposite the first conductivity type.

4. The memory array of claim 1, wherein the antifuse is vertically below the first diode portion.

5. The memory array of claim 1, wherein the antifuse is vertically between the first diode portion and the second diode portion.

6. The memory array of claim 5, wherein

the first diode portion comprises semiconductor material of a first conductivity type, and

the second diode portion comprises semiconductor material of a second conductivity type opposite the first conductivity type.

7. The memory array of claim 6, wherein

the first diode portion comprises a semiconductor-type material or a metal-type material, and

the second diode portion comprises a metal-type material or a semiconductor-type material, wherein the type of material of the second diode portion is the different from the type of the first diode portion.

8. A memory array comprising a plurality of memory cells, each memory cell comprising:

a first diode portion;

a second diode portion wherein the first or the second diode portion comprises in-situ doped polysilicon; and

a dielectric-rupture antifuse comprising silicon nitride in contact with the second diode portion.

9. The memory array of claim 8, wherein

the first diode portion comprises in-situ doped polysilicon and

the second diode portion comprises metal or metal-like material.

10. The memory array of claim 9, wherein the second diode portion comprises a layer of titanium nitride in contact with the antifuse, wherein, for any portion of the titanium nitride layer with a thickness greater than about 20 angstroms, the titanium nitride has a density less than 4.0 grams/cm.

11. The memory array of claim 10, wherein the first diode portion or the second diode portion forms part of a rail-stack.

12. The memory array of claim 10, wherein the first diode portion or the second diode portion forms part of a pillar.

13. The memory array of claim 8, wherein

the first diode portion comprises in-situ doped polysilicon of a first conductivity type and

the second diode portion comprises in-situ doped polysilicon of a second conductivity type opposite the first conductivity type.

14. The memory array of claim 13, wherein the first diode portion or the second diode portion forms part of a rail-stack.

15. The memory array of claim 13, wherein the first diode portion or the second diode portion forms part of a pillar.

16. A monolithic three dimensional memory array comprising:

first conductors extending in a first direction at a first height above a substrate;

second conductors extending in a second direction at a second height above the substrate, wherein the second direction is different from the first direction; and

antifuses comprising silicon nitride.

17. The monolithic three dimensional memory array of claim 16 wherein

the antifuses are in contact with a first metallic material, wherein the first metallic material is titanium nitride, tungsten nitride, tantalum nitride, tantalum tungsten, tungsten, or aluminum.

18. The monolithic three dimensional memory array of claim 17 wherein the first metallic material is titanium nitride, and

for any thickness of titanium nitride greater than about 20 angstroms, the density of the titanium nitride is less than about 4.0 grams/cm³ and the resistivity of the titanium nitride is greater than about 300 microOhm-cms.

19. The monolithic three dimensional memory array of claim 16 wherein the antifuses are at a third height between the first height and the second height.

20. A monolithic three dimensional memory array comprising memory cells, each memory cell comprising:

a first diode portion;

a second diode portion; and

an antifuse comprising silicon nitride.

21. The monolithic three dimensional memory array of claim 20 wherein the second diode portion is formed vertically above the first diode portion

22. The monolithic three dimensional memory array of claim 21 wherein the antifuse is between the first diode portion and the second diode portion.

23. The monolithic three dimensional memory array of claim 21 wherein the antifuse is vertically above the second diode portion.