Ceramic/organic hybrid substrate

• US 20040016996A1
• Filed: 07/26/2002
• Published: 01/29/2004
• Est. Priority Date: 07/26/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Tang, John
• Granted Patent: US 7,714,432 B2
• Time in Patent Office: Days
• US Class Current: 257/678
• CPC Class Codes: H01L 21/481 Insulating layers on insulating parts, with or without metallisation
• CPC Class Codes: H01L 23/15 Ceramic or glass substrates H01L23/142, H01L23/145, H01L23/147 take precedence
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49894 Materials of the insulating layers or coatings
• CPC Class Codes: H01L 2924/15174 in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/19106 in a mirrored arrangement on two different side of a common die mounting substrate

Abstract

A semiconductor device is provided that includes one or more ceramic material layers and one or more low dielectric constant (low-K) epoxy layers on top to be electrically coupled to an integrated circuit device, such as a chip die. The resulting ceramic/organic hybrid substrate takes advantage of the thin low-cost, low-K epoxy layer, by routing the dense circuitry from the chip die to the ceramic material layer. In addition, the use of low-K epoxy layer may reduce the number of ceramic material layers required to about three layers, thus significantly reducing the cost of the substrate. Low-K epoxy material layer may be laminated onto the ceramic material layer to reduce throughput time and cost. The ceramic/organic hybrid substrate may also take advantage of the properties of ceramic materials, which have a much more rigid structure than organic materials and a low CTE (coefficient of thermal expansion) that works well with ultra low-K chip dies. The ceramic/organic hybrid substrate also may make possible the fabrication of a bottom cavity package for capacitors placement.

Claims

1. A semiconductor package, comprising:

at least one ceramic material layer; and

at least one low dielectric constant epoxy layer disposed over said at least one ceramic material layer, wherein said low dielectric constant epoxy layer is to be coupled to an integrated circuit.

2. A semiconductor package as recited in claim 1, wherein the low dielectric constant epoxy layer is an organic film that is laminated onto the ceramic material layer.

3. A semiconductor package as recited in claim 2, wherein the ceramic material layer includes three layers having a thickness of about 450 μ

m.

4. A semiconductor package as recited in claim 3, wherein the low dielectric constant epoxy layer has a thickness of about 30 μ

m.

5. A semiconductor package as recited in claim 4, wherein the low dielectric constant material supports a line space of about 20 microns and the ceramic material layer supports a line space between about 75 microns and about 100 microns.

6. A semiconductor package as recited in claim 4, wherein the ceramic material layer includes an inner bottom surface and an outer bottom surface, wherein said inner bottom surface is recessed relative to said outer bottom surface.

7. A semiconductor package as recited in claim 6, wherein the inner bottom surface is to support a plurality of capacitors.

8. A semiconductor package as recited in claim 7, wherein said inner bottom surface is recessed from said outer bottom surface.

9. A method of forming a semiconductor package, comprising:

providing ceramic material layers; and

laminating low dielectric constant epoxy layers over said ceramic material layer, wherein said dielectric constant material layer is to be coupled to an integrated circuit.

10. A method of forming a semiconductor package as recited in claim 9, further comprising:

screen printing metalization on said ceramic material layer; and

patterning said low dielectric constant epoxy layer.

11. A method of forming a semiconductor package as recited in claim 10, wherein the low dielectric constant epoxy material includes an organic film.

12. A method of forming a semiconductor package as recited in claim 11, wherein the ceramic material layer includes a plurality of layers and has a thickness of about 450 μ

m.

13. A method of forming a semiconductor package as recited in claim 12, wherein the low dielectric constant epoxy layer has a thickness of about 30 μ

m.

14. A method of forming a semiconductor package as recited in claim 13, wherein the low dielectric constant epoxy layer supports a line space of about 20 microns and the ceramic material layer supports a line space between about 75 microns and about 100 microns.

15. A method of forming a semiconductor package as recited in claim 14, wherein the ceramic material layer includes a plurality of layers, the method further comprising:

forming a void in a first of said plurality of layers; and

joining the plurality of layers of said ceramic material layer together to form an inner bottom surface in said void and an outer bottom surface, wherein said inner bottom surface is recessed relative to said outer bottom surface.

16. A method of forming a semiconductor package as recited in claim 15, wherein the inner bottom surface is to support a plurality of capacitors.

17. A semiconductor package, comprising:

ceramic material layers, wherein an inner bottom surface of said ceramic material layer is recessed relative to an outer bottom surface of said ceramic material layer;

low dielectric constant epoxy layers disposed over said ceramic material layer; and

an integrated circuit chip electrically coupled to said low dielectric constant epoxy layer.

18. A semiconductor package as recited in claim 17 further comprising:

a plurality of capacitors electrically coupled to the inner bottom surface of said ceramic material layer.

19. A semiconductor package as recited in claim 18 wherein said inner bottom surface of said ceramic material layer is recessed 150 μ

m from said outer bottom surface.

20. A semiconductor package as recited in claim 19, wherein the low dielectric constant epoxy layer is an organic film that is laminated onto the top ceramic material layer.

21. A semiconductor package as recited in claim 20, wherein the low dielectric constant epoxy layer has a thickness of about 30 μ

m.

22. A semiconductor package as recited in claim 21, wherein the low dielectric constant epoxy layer supports a line space of about 20 microns and the ceramic material layer supports a line space between about 75 microns and about 100 microns.

23. The semiconductor package as recited in claim 22 further comprising:

a plurality of pins coupled to said outer bottom surface of said ceramic material layer.

24. The semiconductor package as recited in claim 23 further comprising:

solder coupled to said outer bottom surface of said ceramic material layer.