Integrated circuit and sensor for imaging

• US 20040017224A1
• Filed: 03/05/2003
• Published: 01/29/2004
• Est. Priority Date: 03/05/2002
• Status: Active Grant

• Current Assignee: Nova R&D Incorporated (Kromek Group PLC)
• Original Assignee: Nova R&D Incorporated (Kromek Group PLC)
• Inventors: Calderwood, Robert F., Visser, Gerard, Clajus, Martin, Tumer, Tumay O.
• Granted Patent: US 7,868,665 B2
• Time in Patent Office: Days
• US Class Current: 327/51
• CPC Class Codes: G01T 1/171 Compensation of dead-time counting losses see provisionally also G01T1/17
• CPC Class Codes: H03F 2200/331 Sigma delta modulation being used in an amplifying circuit
• CPC Class Codes: H03F 3/087 with IC amplifier blocks H03F3/085 takes precedence
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit

Abstract

New sensors and different embodiments of multi-channel integrated circuit are provided. The new high energy and spatial resolution sensors use both solid state and scintillator detectors. Each channel of the readout chip employs low noise charge sensitive preamplifier(s) at its input followed by other circuitry. The different embodiments of the sensors and the integrated circuit are designed to produce high energy and/or spatial resolution two-dimensional and three-dimensional imaging for widely different applications. Some of these applications may require fast data acquisition, some others may need ultra high energy resolution, and a separate portion may require very high contrast. The embodiments described herein addresses all these issues and also other issues that may be useful in two and three dimensional medical and industrial imaging. The applications of the new sensors and integrated circuits addresses a broad range of applications such as medical and industrial imaging, NDE and NDI, security, baggage scanning, astrophysics, nuclear physics and medicine.

Claims

1. A data readout integrated circuit comprising a plurality of inputs coupled to a plurality of detectors, plurality of inputs coupled to plurality of input amplifiers, for providing a plurality of readout signals amplified from the plurality of detector signals, each input amplifier is part of a readout channel of said plurality, said readout channels comprising:

a means for receiving one detector signal;

a charge sensitive amplifier coupled to said receiving means for integrating said detector signal and outputting a voltage signal;

a comparator circuit for discriminating the said charge sensitive amplifier output,

a counter for counting the said discriminated pulses from the charge sensitive amplifier output, and

a means for outputting said counter contents responsive to said detector signals.

2. The data readout integrated circuit of claim 1, wherein a polarity switching circuit is included.

3. The data readout integrated circuit of claim 2, wherein said polarity switching circuit is externally controlled.

4. The data readout integrated circuit of claim 1, further comprising a gain stage coupled to said charge sensitive amplifier.

5. The data readout integrated circuit of claim 1, further comprising a shaper amplifier for providing shaped, integrated detector signals responsive to said selected signal.

6. The data readout integrated circuit of claim 5, wherein said shaped, integrated detector signal is of an approximately inverted bell shaped form.

7. The data readout integrated circuit of claim 5, wherein said shaped, integrated detector signal is of an approximate uninverted bell shaped form.

8. The data readout integrated circuit of claim 5, further comprising a register circuit coupled to the said counters, wherein the register keeps the counter contents until read out while counter starts counting again.

9. The data readout integrated circuit of claim 8, wherein a first comparator of said plurality of comparators is a low level discriminator, and wherein at least one of said first comparator allows an output trigger when a peak hold circuit output is larger than a first threshold voltage.

10. The data readout integrated circuit of claim 9, further comprising a second comparator of said plurality of comparators wherein said second comparator is an higher level discriminator, and wherein said second comparator only issues a signal when said peak hold circuit output is larger than a second threshold voltage.

11. The data readout integrated circuit of claim 10, wherein said first comparator and said second comparator enclose at least one predetermined energy band.

12. The data readout integrated circuit of claim 10, further comprising a differentiator circuit coupled to at least one of said first plurality of comparators, said differentiator circuit producing a fast trigger output with low jitter.

13. The data readout integrated circuit of claim 8, wherein an output of said peak hold circuit is multiplexed to said means for outputting.

14. The data readout integrated circuit of claim 10, wherein an output of at least one of said comparator or said second plurality of comparator initiates a readout cycle of said data readout integrated circuit.

15. The data readout integrated circuit of claim 1, wherein said data outputting means outputs a readout signal for one channel of said plurality of integrated circuit channels containing a detected signal.

16. The data readout integrated circuit of claim 15, wherein said data outputting means only outputs said readout signal for said channel of said plurality of integrated circuit channels for which a trigger signal has been received.

17. The data readout integrated circuit of claim 15, wherein said data outputting means outputs said readout signal for said channel of said plurality of integrated circuit channels after said trigger signal has been received for any one of said plurality of integrated circuit channels.

18. The data readout integrated circuit of claim 17, wherein said trigger signal is an external trigger signal.

19. The data readout integrated circuit of claim 1, wherein said data outputting means output a readout signal for one triggered channel of said plurality of integrated circuit channels an disables all remaining channels of said plurality of integrated circuit channels, wherein a time delay between said readout signal and said disablement of said remaining channels is controlled by an externally supplied signal.

20. The data readout integrated circuit of claim 1, wherein said input charge sensitive amplifier has a resistive feedback in parallel to the capacitance feedback.