Sub-micron high input voltage tolerant input output (I/O) circuit

• US 20040017229A1
• Filed: 07/16/2003
• Published: 01/29/2004
• Est. Priority Date: 01/09/2001
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Ajit, Janardhanan S.
• Granted Patent: US 6,949,964 B2
• Time in Patent Office: Days
• US Class Current: 327/112
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 19/01818 for integrated injection logic (I2L)
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependant on the external voltages seen by the low voltage integrated circuit.

Claims

1. An apparatus for providing an input output from an integrated circuit, the apparatus comprising:

an input/output (I/O) pad;

an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices, a first of the upper PMOS devices having source coupled to a power supply (V_DDO) and drain coupled to source of a second upper PMOS device, the second PMOS device having drain coupled to the I/O pad;

a lower pair of N-channel MOS devices (NMOS), a first of the upper NMOS devices having a drain coupled to the I/O pad and a source coupled to a drain of a second lower NMOS device, the second NMOS device having a source coupled to a ground potential;

a first bias circuit coupled to a gate of the first upper PMOS device, said bias circuit providing a first bias voltage to the gate of the first upper PMOS device when the I/O pad is in an output mode and V_DDO voltage otherwise;

a second bias circuit coupled to a gate of the second lower NMOS device, said bias circuit providing a second bias voltage to the gate of the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise;

a third bias circuit coupled to a gate of the second upper PMOS device, said bias circuit providing a third bias voltage, coupled to the gate of the second upper MOS device; and

a fourth bias circuit coupled to a gate of the first lower NMOS device, said bias circuit providing a fourth bias voltage to the gate of the first lower MOS device, the fourth bias voltage being in a range, the range having a maximum value of V_DDP+V_T and a minimum value of (V_DDO −

V_Tp), where V_DDP and V_DDO are power supply voltages and V_T and V_Tp are offset voltages.

2. The apparatus of claim 1 wherein V_DDO and V_DDP are the same power supply.

3. The apparatus of claim 1 wherein V_T and V_Tp are the same offset voltages.

4. An apparatus for providing an input output from an integrated circuit, the apparatus comprising:

an input/output (I/O) pad;

an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices, a first of the upper PMOS devices having source coupled to a power supply (V_DDO)and drain coupled to source of a second upper PMOS device, the second PMOS device having drain coupled to the I/O pad;

a lower pair of N-channel MOS devices (NMOS), a first of the upper NMOS devices having a drain coupled to the I/O pad and a source coupled to a drain of a second lower NMOS device, the second NMOS device having a source coupled to a ground potential;

a first bias circuit coupled to a gate of the first upper PMOS device, said bias circuit providing a first bias voltage to the gate of the first upper PMOS device when the I/O pad is in an output mode and V_DDO voltage otherwise;

a second bias circuit coupled to a gate of the second lower NMOS device, said bias circuit providing a second bias voltage to the gate of the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise;

a third bias circuit coupled to a gate of the second upper PMOS device, said bias circuit providing a third bias voltage to the gate of the second upper MOS device; and

a fourth bias circuit coupled to a gate of the first lower NMOS device, said bias circuit providing a fourth bias voltage to the gate of the first lower MOS device depending on the voltage on the I/O pad (V_PAD) when the pad is in an output disable mode, and said bias circuit providing a fixed fourth bias voltage to the gate of the first lower MOS device when the pad is in an output enable mode.

5. The apparatus of claim 4 wherein the fixed fourth bias voltage is V_DDP.

6. An apparatus for providing an input output from an integrated circuit, the apparatus comprising:

an input/output (I/O) pad;

an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices, a first of the upper PMOS devices having source coupled to a power supply (V_DDO)and drain coupled to source of a second upper PMOS device, the second PMOS device having drain coupled to the I/O pad;

a lower pair of N-channel MOS devices (NMOS), a first of the upper NMOS devices having a drain coupled to the I/O pad and a source coupled to a drain of a second lower NMOS device, the second NMOS device having a source coupled to a ground potential;

a first bias circuit coupled to a gate of the first upper PMOS device, said bias circuit providing a first bias voltage to the gate of the first upper PMOS device when the I/O pad is in an output mode and V_DDO voltage otherwise;

a second bias circuit coupled to a gate of the second lower NMOS device, said bias circuit providing a second bias voltage to the gate of the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise;

a third bias circuit coupled to a gate of the second upper PMOS device, said bias circuit providing a third bias voltage to the gate of the second upper MOS device equal to the voltage on the I/O pad (V_PAD)when the pad is in an output disable mode, and where the third bias voltage to the gate of the second upper MOS device equal to a fixed voltage when the pad is in an output enabled mode; and

a fourth bias circuit coupled to a gate of the first lower NMOS device, said bias circuit providing a fourth bias voltage to the gate of the first lower MOS device.

7. The apparatus of claim 6 wherein the fixed voltage is V_DDC.

8. An apparatus for providing an input output from an integrated circuit, the apparatus comprising:

an input/output (I/O) pad;

an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices, a first of the upper PMOS devices having source coupled to a power supply (V_DDO)and drain coupled to source of a second upper PMOS device, the second PMOS device having drain coupled to the I/O pad;

a lower pair of N-channel MOS devices (NMOS), a first of the upper NMOS devices having a drain coupled to the I/O pad and a source coupled to a drain of a second lower NMOS device, the second NMOS device having a source coupled to a ground potential;

a first bias circuit coupled to a gate of the first upper PMOS device, said bias circuit providing a first bias voltage to the gate of the first upper PMOS device when the I/O pad is in an output mode and V_DDO voltage otherwise;

a second bias circuit coupled to a gate of the second lower NMOS device, said bias circuit providing a second bias voltage to the gate of the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise;

a third bias circuit coupled to a gate of the second upper PMOS device, said bias circuit providing a third bias voltage to the gate of the second upper MOS device; and

a fourth bias circuit coupled to a gate of the first lower NMOS device, said bias circuit providing a fourth bias voltage to the gate of the first lower MOS device depending on the voltage on the I/O pad (V_PA), said fourth bias circuit comprising a capacitive voltage divider.

9. The apparatus of claim 8 wherein the capacitive voltage divider proportions the difference between a pad and power supply voltage to derive the fourth bias voltage, when a voltage provided to the pad is changing.

10. An apparatus for providing an input output from an integrated circuit, the apparatus comprising:

an input/output (I/O) pad;

an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices, a first of the upper PMOS devices having source coupled to a power supply (V_DDO)and drain coupled to source of a second upper PMOS device, the second PMOS device having drain coupled to the I/O pad;

a lower pair of N-channel MOS devices (NMOS), a first of the upper NMOS devices having a drain coupled to the I/O pad and a source coupled to a drain of a second lower NMOS device, the second NMOS device having a source coupled to a ground potential;

a first bias circuit coupled to a gate of the first upper PMOS device, said bias circuit providing a first bias voltage to the gate of the first upper PMOS device when the I/O pad is in an output mode and V_DDO voltage otherwise;

a second bias circuit coupled to a gate of the second lower NMOS device, said bias circuit providing a second bias voltage to the gate of the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise;

a third bias circuit coupled to a gate of the second upper PMOS device, said bias circuit providing a third bias voltage to the gate of the second upper MOS device depending on the voltage on the I/O pad (V_PAD) said third bias circuit comprising a capacitive voltage divider; and

a fourth bias circuit coupled to a gate of the first lower NMOS device, said bias circuit providing a fourth bias voltage to the gate of the first lower MOS device.

11. The apparatus of claim 10 wherein the capacitive voltage divider proportions a difference in voltage at the pad and a power supply voltage to derive the third bias voltage when the pad is switching.