On chip network

• US 20040017820A1
• Filed: 07/29/2002
• Published: 01/29/2004
• Est. Priority Date: 07/29/2002
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Walker, Gary A., Garinger, Ned D., Dorr, Martin L., Naumann, Mark W.
• Granted Patent: US 7,277,449 B2
• Time in Patent Office: Days
• US Class Current: 370/419
• CPC Class Codes: H04L 49/101 using crossbar or matrix
• CPC Class Codes: H04L 49/102 using shared medium, e.g. bus or ring
• CPC Class Codes: H04L 49/109 Integrated on microchip, e.g. switch-on-chip
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports

Abstract

An OCN for integrated processing elements including a network with multiple ports and multiple port interfaces. The ports and the port interfaces conform to a consistent port protocol. Each port interface converts information between bus transactions of a corresponding processing element and network packets and exchanges network packets with other port interfaces. Each port includes an arbitration interface and a data interface and the network includes an interconnect and an arbiter. The interconnect includes selectable data paths between the ports for packet datum transfer. A port source interface submits transaction requests and provides packet datums upon receiving an acknowledgement. A port destination interface receives packet datums via available input buffers. Each transaction request includes a transaction size and a destination port address. The arbiter receives transaction requests, arbitrates among transaction requests, provides acknowledgements and controls the interconnect to select data paths between sources and destinations.

Claims

1. An on chip network (OCN) for enabling communications between a plurality of processing elements integrated on a chip, comprising:

a network having a plurality of ports, each port conforming to a consistent port protocol for transferring network packets between ports; and

a plurality of port interfaces, each coupled to a corresponding port and configured to convert information between bus transactions of a corresponding processing element and network packets, each port interface configured to operate in conformance with the consistent port protocol to exchange network packets with other port interfaces via the network.

2. The OCN of claim 1, further comprising:

each port including an arbitration interface and a data interface; and

the network comprising;

an interconnect having selectable data paths between any of the plurality of ports in which a source port data output is coupled to a destination port data input for an acknowledged transaction; and

an arbiter, coupled to the interconnect and to the plurality of ports, that receives a plurality of transaction requests and provides corresponding acknowledgements via the arbitration interfaces of the ports, that arbitrates among a plurality of transaction requests, and that controls the interconnect to select data paths between source and destination ports for acknowledged transactions.

3. The OCN of claim 2, wherein the interconnect has a maximum datum width and wherein each packet comprises one or more datums having a size up to the maximum datum width.

4. The OCN of claim 2, wherein the interconnect comprises a cross-bar switch.

5. The OCN of claim 2, wherein the interconnect comprises an AND-OR bus structure.

6. The OCN of claim 2, wherein each port interface comprises:

a source port interface, coupled to the arbitration interface and a data interface output of a corresponding port, that sends transaction requests and receives acknowledgements via the arbitration interface, and that sends a packet via the data interface output upon receiving a corresponding acknowledgement; and

a destination port interface that receives a packet into a packet buffer via a corresponding port data input.

7. The OCN of claim 6, wherein packets are transferred synchronously from a source port data output to a destination port data input in which each packet datum is clocked through the interconnect upon consecutive clock cycles of an interface clock for an acknowledged transaction.

8. The OCN of claim 6, wherein:

the interconnect has a maximum datum width;

wherein each packet comprises one or more datums having a size up to the maximum datum width;

wherein the source port interface provides each datum of a packet on consecutive clock cycles via a corresponding data output beginning at a clock cycle in which an acknowledgement is received;

wherein the arbiter provides data enable signals to each destination port interface during a clock cycle when packet datums arrive from the interconnect; and

wherein each destination port interface receives all packet datums on consecutive clock cycles beginning when data enable signals are provided from the arbitrer.

9. The OCN of claim 8, wherein a data input and data output of each data interface of each port includes an end of packet (EOP) sideband signal, and wherein a source port interface asserts an EOP signal at the source port data output coincident with the last datum of a packet so that a corresponding EOP signal at the destination data input is asserted coincident with the last datum of the packet.

10. The OCN of claim 8, wherein the arbiter further comprises:

a plurality of destination buffer counters, each identifying a number of destination buffers at a corresponding destination port interface; and

at least one packet datum counter, each packet datum counter tracking packet datum progress through the interconnect for an acknowledged transaction.

11. An integrated circuit (IC), comprising:

a plurality of processing elements;

a network including a plurality of ports, each port conforming to a consistent port protocol for transferring network packets between ports; and

a plurality of port interfaces, each port interface coupled to a corresponding port and to a corresponding processing element and configured to convert information between processing element bus transactions and network packets, and each port interface operating in conformance with the consistent port protocol to exchange network packets with other port interfaces via the network.

12. The IC of claim 11, further comprising:

each port including an arbitration interface and a data interface having a data input and a data output; and

the network comprising;

an interconnect having selectable data paths between any of the plurality of ports in which a source port data output is coupled to a destination port data input for an acknowledged transaction; and

an arbiter, coupled to the interconnect and to the plurality of ports, that receives a plurality of transaction requests and provides corresponding acknowledgements via the arbitration interfaces of the ports, that arbitrates among a plurality of transaction requests, and that controls the interconnect to select data paths between source and destination ports for acknowledged transactions.

13. The IC of claim 12, wherein the interconnect has a maximum datum width and wherein each packet comprises one or more datums having a size up to the maximum datum width.

14. The IC of claim 12, wherein each port interface comprises:

a source port interface, coupled to the arbitration interface and the data output of a corresponding port, that sends transaction requests and receives acknowledgements via the arbitration interface, and that sends a packet via the port data output upon receiving a corresponding acknowledgement; and

a destination port interface that receives a packet into a packet buffer via the corresponding port data input.

15. The IC of claim 14, wherein packets are transferred synchronously from a source port data output to a destination port data input in which each packet datum is clocked through the interconnect upon consecutive clock cycles of an interface clock for an acknowledged transaction.

16. The IC of claim 14, wherein:

the interconnect has a maximum datum width;

wherein each packet comprises one or more datums having a size up to the maximum datum width;

wherein the source port interface provides each datum of a packet on consecutive clock cycles via its data output beginning at a clock cycle in which an acknowledgement is received;

wherein the arbiter provides data enable signals to each destination port interface during a clock cycle when packet datums arrive from the interconnect; and

wherein each destination port interface receives all packet datums on consecutive clock cycles beginning when data enable signals are provided from the arbitrer.

17. The IC of claim 12, wherein the arbiter further comprises:

a plurality of destination buffer counters, each identifying a number of destination buffers at a corresponding destination port interface; and

at least one packet datum counter, each packet datum counter tracking packet datum progress through the interconnect for an acknowledged transaction.

18. An communication system for enabling communications between a plurality of processing elements integrated on a chip, comprising:

a plurality of ports, each including an arbitration interface and a data interface and each operating according to a predetermined port protocol;

an interconnect, coupled to the plurality of ports, that transfers network packets between ports; and

a plurality of bus gaskets, each coupled to a corresponding port and operating according to the predetermined protocol, each bus gasket configured to convert information between bus transactions of a corresponding processing element and network packets and arbitrating for the interconnect to send network packets to other bus gaskets.

19. The communication system of claim 18, further comprising:

the interconnect having selectable data paths between any of the ports in which a source port data output is coupled to a destination port data input for an acknowledged transaction; and

an arbiter, coupled to the interconnect and to the plurality of ports, that receives and arbitrates among a plurality of transaction requests, that provides corresponding acknowledgements via the arbitration interfaces of the ports, and that controls the interconnect to select data paths between source and destination ports for acknowledged transactions.

20. The communication system of claim 18, wherein the interconnect comprises a cross-bar switch that enables a plurality of concurrent transactions.