Method of filling an opening in a material layer with an insulating material

• US 20040018696A1
• Filed: 03/31/2003
• Published: 01/29/2004
• Est. Priority Date: 07/26/2002
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Kruegel, Stephan, Wieczorek, Karsten, Raab, Michael
• Granted Patent: US 6,812,115 B2
• Time in Patent Office: Days
• US Class Current: 438/431
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: Y10S 438/933 Germanium or silicon or Ge-Si on III-V

Abstract

The filling of sub-0.25 μm trenches with dielectric material may lead to the formation of a void. Typically, the void may be closed by oxidation. When the trench includes non-oxidizable sidewall portions, insufficient closure may result. Therefore, an oxidizable spacer layer is conformally deposited prior to depositing the bulk dielectric, so that the sidewalls of the trench may be oxidized along the entire depth of the trench, thereby allowing the complete closure of the void.

Claims

1. A method of filling a trench formed in a substrate, the method comprising:

conformally depositing a spacer layer comprised of oxidizible material on said substrate and in said trench;

depositing a dielectric material over said spacer layer to fill said trench; and

performing an oxidation process in an oxidizing ambient to convert at least a portion of said spacer layer into an insulating layer.

2. The method of claim 1, wherein said spacer layer is substantially completely oxidized.

3. The method of claim 1, further comprising anisotropically etching said spacer layer prior to depositing said dielectric material.

4. The method of claim 3, further comprising forming an etch stop layer prior to depositing said spacer layer.

5. The method of claim 1, wherein performing said oxidation process converts at least a portion of said spacer layer to silicon dioxide.

6. The method of claim 4, wherein said spacer layer is anisotropically etched to form sidewall spacers in said trench.

7. The method of claim 1, wherein said substrate comprises at least one non-oxidizable insulating layer formed thereon, whereby said trench is formed in said at least one insulating layer and partially in said substrate.

8. The method of claim 1, wherein said trench has at least one lateral dimension of 0.25 μ

m or less.

9. The method of claim 1, wherein a depth of said trench is in the range of approximately 200-700 nm.

10. The method of claim 1, wherein said substrate comprises a semiconductor layer and a non-oxidizable insulating layer formed on said semiconductor layer, whereby said trench is formed in said insulating layer and at least partially in said semiconductor layer.

11. The method of claim 10, wherein said semiconductor layer comprises at least one of silicon and germanium.

12. The method of claim 10, wherein said insulating material comprises silicon nitride.

13. The method of claim 1, wherein said dielectric material is an oxide of a semiconductive material.

14. A method of filling a trench formed in a substrate with a dielectric material, the method comprising:

forming spacer elements on sidewalls of said trench, said spacer elements being comprised of an oxidizable material;

depositing a dielectric material over said substrate to substantially fill said trench; and

exposing said substrate to an oxidizing ambient to convert at least a portion of said spacer elements into an insulating layer.

15. The method of claim 14, wherein forming said spacer elements comprises depositing a spacer layer on said substrate and in said trench and anisotropically etching said spacer layer to remove said spacer layer at the bottom of said trench.

16. The method of claim 15, further comprising forming an etch stop layer prior to depositing said spacer layer.

17. The method of claim 16, wherein said etch stop layer is formed by oxidizing said substrate to form an oxide layer within said trench.

18. The method of claim 14, wherein said substrate comprises an insulating layer stack formed on a semiconductive layer, wherein said trench is formed in said insulating layer stack and at least partially in said semiconductive layer.

19. The method of claim 18, wherein said insulating layer stack comprises a silicon nitride layer and a silicon oxide layer.

20. The method of claim 15, wherein a thickness of said spacer layer is in the range of approximately 5-100 nm.

21. A method of filling a trench in a substrate, said substrate comprising a layer of a semiconductive material and a layer of a dielectric material formed thereon, said method comprising:

forming sidewall spacers of a semiconductive material in said trench, the sidewall spacers covering non-oxidizable sidewall portions of said trench;

filling said trench with a dielectric material; and

exposing said substrate to an oxidizing ambient to at least partially oxidize said sidewall spacers.

22. The method of claim 21, wherein forming said sidewall spacers in the trench comprises conformally depositing a second layer of a semiconductive material on said substrate.

23. The method of claim 22, further comprising anisotropically etching said second layer of semiconductive material so as to remove said second semiconductive material from areas of said substrate outside said trench and from a bottom of said trench.

24. The method of claim 23, wherein filling said trench with a dielectric material comprises depositing a second layer of a dielectric material on said substrate.

25. The method of claim 24, further comprising forming an oxide layer inside said trench prior to conformally depositing said second layer of a semiconductive material.

26. The method of claim 25, wherein oxidizing said spacers comprises subjecting said substrate to a thermal oxidation process at a temperature in the range of approximately 600-1100°

C.

27. The method of claim 22, wherein said second layer of a semiconductive material is deposited by one of a sub-atmospheric chemical vapor deposition process and a high density plasma-enhanced chemical vapor deposition process.

28. The method of claim 24, wherein said second layer of a dielectric material is deposited by one of a sub-atmospheric chemical vapor deposition process and a high density plasma-enhanced chemical vapor deposition process.

29. The method of claim 23, wherein said layer of semiconductive material and said second layer of semiconductive material comprise silicon.

30. The method of claim 24, wherein said layer of dielectric material and said second layer of dielectric material comprise silicon dioxide.

31. A method of forming an isolation structure in a substrate comprising a semiconductive layer and a dielectric layer stack formed on said semiconductive layer, the method comprising:

forming a trench in said substrate, said trench extending in a depth dimension through said dielectric layer stack;

conformally depositing a spacer layer on said substrate, said spacer layer being comprised of an oxidizable material;

depositing a dielectric material for filling said trench; and

exposing said substrate to an oxidizing ambient to at least partially oxidize said spacer layer to fill any void that may have formed during the deposition of said dielectric material.

32. The method of claim 31, further comprising anisotropically etching said spacer layer prior to depositing said dielectric material to form sidewall spacers on sidewalls of said trench.

33. The method of claim 32, further comprising forming an etch stop layer prior to depositing said spacer layer.

34. The method of claim 31, wherein one lateral dimension of said trench is 0.25 μ

m or less.

35. The method of claim 31, wherein said dielectric material is a semiconductor oxide.

36. The method of claim 31, wherein said spacer layer comprises one of silicon and germanium.

37. The method of claim 31, wherein a thickness of said spacer layer is in the range of approximately 5-100 nm.

38. A method of forming shallow trench isolation structures in a substrate of a semiconductive material during a manufacturing process for manufacturing integrated circuits, said method comprising:

forming a first layer of dielectric material on said substrate of semiconductive material;

selectively etching said first layer of dielectric material and said substrate of semiconductor material so as to form trenches deeper than the thickness of said layer of dielectric material, said trenches having sidewalls;

forming sidewall spacers comprised of a semiconductive material in said trenches, said spacers covering the inside sidewalls of said trenches;

filling said trenches with a dielectric material; and

oxidizing said sidewall spacers along the entire depth of said trench sidewalls.

39. The method of claim 38, wherein forming said sidewall spacers in said trenches comprises conformally depositing a second layer of a semiconductive material on said first layer of dielectric material to a thickness allowing complete sidewall coverage inside said trenches.

40. The method of claim 39, further comprising anisotropically etching said second layer of a semiconductive material so as to remove said semiconductive material from the areas of said first layer of dielectric material outside said trenches and from the bottom of said trenches.

41. The method of claim 40, wherein filling said trenches with a dielectric material comprises depositing a third layer of a dielectric material on said first layer of dielectric material.

42. The method of claim 38, further comprising thermal growing of a liner layer of dielectric material inside said trenches prior to conformally depositing said second layer of a semiconductive material.

43. The method of claim 38, wherein oxidizing said spacers is performed at a temperature in the range of about 600-1100°

C.

44. The method of claim 38, wherein said second layer of a semiconductive material is deposited by a sub-atmospheric chemical vapor deposition process.

45. The method of claim 44, wherein said third layer of a dielectric material is deposited according to one of a sub-atmospheric chemical vapor deposition process and a high density plasma-enhanced chemical vapor deposition process.

46. The method of claim 39, wherein said semiconductive material of said substrate and said second layer comprises silicon.

47. The method of claim 39, wherein said dielectric material of said third layer comprises silicon dioxide.