Methods for fabricating three dimensional integrated circuits

• US 20040018711A1
• Filed: 10/08/2002
• Published: 01/29/2004
• Est. Priority Date: 07/08/2002
• Status: Abandoned Application

• Current Assignee: Liberty Patents LLC
• Original Assignee: Liberty Patents LLC
• Inventors: Madurawe, Raminda U.
• Application Number:
  US10/267,484
• Publication Number:
  US 20040018711A1
• Time in Patent Office: Days
• US Class Current: 438/598
• CPC Class Codes: H01L 21/44 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]

Abstract

A method for forming a semiconductor device includes fabricating one or more digital circuits on a substrate; selectively fabricating either a memory circuit or a conductive pattern substantially above the digital circuits to control portion of digital circuits; and fabricating an interconnect and routing layer substantially above the digital circuits and memory circuits to connect digital circuits and one of the memory circuit or the conductive pattern.

Claims

1. A method of forming a semiconductor device, comprising:

fabricating one or more digital circuits on a substrate;

selectively fabricating either a memory circuit or a conductive pattern substantially above the digital circuits to control portion of digital circuits; and

fabricating an interconnect and routing layer substantially above the digital circuits and memory circuits to connect digital circuits and one of the memory circuit or the conductive pattern.

2. The method of claim 1, wherein the digital circuits contain logic blocks.

3. The method of claim 2, wherein the memory circuit contains programmable memory to configure logic blocks to a user specification.

4. The method of claim 2, wherein the conductive pattern contains hard-wired controls to configure logic blocks.

5. The method of claim 1, further comprising fabricating a generic field programmable gate array (FPGA) with the constructed memory circuit.

6. The method of claim 1, further comprising fabricating an application specific integrated circuit (ASIC) with the constructed conductive pattern.

7. The method of claim 6, further comprising fabricating multiple ASICs with different variations of conductive patterns.

8. The method of claim 1, wherein a given configuration of the memory circuit and the corresponding conductive pattern have one or more substantially matching logic control characteristics.

9. The method of claim 8, wherein one or more of the circuit characteristics comprises timing characteristics substantially unchanged by the circuit control option.

10. The method of claim 1, further comprising mapping data stored in the memory circuit to the conductive pattern.

11. The method of claim 10, further comprising generating a mask corresponding to the conductive pattern to fabricate an ASIC.

12. The method of claim 11, further comprising utilizing a logic process sequence.

13. The method of claim 12, wherein the logic process sequence further comprises:

forming a P-type substrate;

creating a twin well;

developing a shallow trench isolation;

performing a sacrificial oxide;

generating a PMOS Vt mask and implant;

generating a NMOS Vt mask and implant;

developing gate oxidation;

depositing gate poly (GP);

applying the GP mask and etch;

applying an LDN mask and implant;

applying an LDP mask and implant;

depositing a spacer oxide and etching the spacer oxide;

depositing Nickel;

performing RTA anneal —

Ni salicidation (S/D/G regions &

interconnect) etching to remove unreacted Nickel;

depositing ILD oxide and performing CMP;

applying a C1 mask and etch;

forming a W plug and performing CMP;

depositing M1;

applying a M1 mask &

etch; and

performing back end metallization.

14. The method of claim 1, further comprising a thin-film transistor (TFT) process sequence.

15. The method of claim 14, wherein the TFT process sequence further comprises:

depositing amorphous poly-1 (P1);

performing P1 mask &

etch;

applying NMOS Vt mask &

P−

implant;

applying PMOS Vt mask &

N−

implant;

depositing Gox;

applying buried contact mask &

etch;

depositing amorphous poly-2 (P2);

applying P2 mask &

etch;

applying LDN mask &

N−

implant;

applying LDP mask &

P−

implant;

depositing Gox;

depositing a spacer oxide and etching the spacer oxide;

applying N+ mask &

implanting NMOS G/S/D;

applying P+ mask &

implanting PMOS G/S/D;

depositing Nickel;

salicidizing the Nickel on the G/S/D regions &

interconnect;

performing RTA anneal—

P1 and P2 re-crystallization;

depositing ILD oxide &

CMP;

applying C2 mask &

etch; and

forming a W plug &

CMP.

16. The method of claim 14, wherein the TFT process sequence is inserted to the logic sequence prior to depositing M1 step.

17. A method of forming a semiconductor device, comprising:

fabricating one or more digital circuits on a first plane; and

selectively fabricating either a memory circuit or a conductive pattern on a second plane to control a portion of the digital circuits; and

fabricating an interconnect and routing layer in a third plane above the first and second planes to connect digital circuits and either memory circuits or conductive patterns.

18. The method of claim 17, further comprising fabricating a field programmable gate array (FPGA) with the memory circuit.

19. The method of claim 17, further comprising fabricating an application specific integrated circuit (ASIC) with the conductive pattern.

20. The method of claim 17, wherein the memory circuit and the conductive pattern have one or more substantially matching logic control characteristics.

21. The method of claim 20, wherein one or more of the circuit characteristics comprises timing characteristics substantially unchanged by the circuit control option.

22. The method of claim 17, further comprising mapping data stored in the memory circuit to the conductive pattern.

23. The method of claim 22, further comprising generating a mask corresponding to the conductive pattern to fabricate an ASIC.

24. The method of claim 17, wherein depositing the memory circuit further comprises depositing a thin-film transistor (TFT).

25. A method to fabricate a programmable logic device, comprising:

constructing one or more digital circuits on a substrate; and

constructing a non-planar circuit on the substrate after constructing the digital circuits, the non-planar circuit being either a memory deposited to store data to configure the digital circuits to form a field programmable gate array (FPGA) or a conductive pattern deposited to hard-wire the digital circuits to form an application specific integrated circuit (ASIC), wherein the deposited memory and the conductive pattern have substantially matching timing characteristics.

26. A method of forming a semiconductor device, comprising:

fabricating one or more digital circuits on a first plane; and

selectively fabricating either a configuration circuit or a conductive pattern on a second plane to control a portion of the digital circuits; and

fabricating an interconnect and routing layer in a third plane above the first and second planes to connect the digital circuits and either the configuration circuit or the conductive pattern.

27. The method of claim 26, wherein fabricating the configuration circuit further comprises depositing a thin-film device.