Sharing data using a configuration register

• US 20040019777A1
• Filed: 04/29/2003
• Published: 01/29/2004
• Est. Priority Date: 06/14/2002
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wygant, Laurance F.
• Application Number:
  US10/426,119
• Publication Number:
  US 20040019777A1
• Time in Patent Office: Days
• US Class Current: 713/1
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes

Abstract

A first execution thread disabling configuration access to a register that is otherwise dedicated to a storage of a configuration parameter, the first execution thread storing data other than the configuration parameter in the register and a second execution thread accessing the data from the register.

Claims

1. A method comprising:

a first execution thread disabling configuration access to a register that is otherwise dedicated to a storage of a configuration parameter;

the first execution thread storing data other than the configuration parameter in the register; and

a second execution thread accessing the data from the register.

2. The method of claim 1 further comprising one of the first execution thread and the second execution thread enabling configuration access to the register after the data other than the configuration parameter in the register has been accessed.

3. The method of claim 2 wherein

disabling configuration access to the register further comprises

changing a status indicator to indicate that the register is unavailable for configuration use;

saving the contents of the register; and

wherein

enabling configuration access to the register further comprises restoring saved contents, if any, to the register; and

changing the status indicator to indicate that the register is available for configuration use.

4. The method of claim 3 wherein the register is an address register normally dedicated to enabling access to the configuration address space a device on a bus.

5. The method of claim 4 wherein the first execution thread executes on a first processor of a multiprocessor system, and wherein the second execution thread executes on a second processor of the multiprocessor system.

6. The method of claim 4 wherein changing the status indicator to indicate that the register is unavailable for configuration use comprises storing a first value in an enable bit of the register;

and wherein changing the status indicator to indicate that the register is available for configuration use comprises storing a second value distinct from the first value in the enable bit of the register.

7. The method of claim 1 further comprising the first execution thread setting a bit of the register to a fixed value after an event occurs and the second execution thread accessing the bit of the register to determine if the event has occurred.

17. A machine-readable medium comprising instructions that when accessed by a machine, cause it to perform the method of claim 1.

18. The machine-readable medium of claim 17 further comprising instructions that when accessed by a machine, cause it to perform the method of claim 2.

19. The machine-readable medium of claim 18 further comprising instructions that when accessed by a machine, cause it to perform the method of claim 3.

20. A machine-readable medium comprising instructions that when accessed by a machine, cause it to perform the method of claim 5.

21. The machine-readable medium of claim 20 further comprising instructions that when accessed by a machine, cause it to perform the method of claim 6.

22. A machine-readable medium comprising instructions that when accessed by a machine, cause it to perform the method of claim 7.

8. A method comprising:

a first execution thread storing data other than a PCI Configuration Address in an address field of a PCI Configuration Address Port; and

a second execution thread reading the data from the address field of the PCI Configuration Address Port.

9. The method of claim 8 wherein the first execution thread executes on a first processor of a multiprocessor system and the second execution thread executes on a second processor of the multiprocessor system.

10. The method of claim 8 further comprising:

the first execution thread clearing the Enable bit of the PCI Configuration Address Port prior to storing the data in the address field of the PCI Configuration Address Port.

11. The method of claim 10 further comprising one of the first execution thread or the second execution thread setting the Enable bit after the data from the address field of the PCI Configuration Address port has been accessed.

12. The method of claim 8 wherein the data is the state of a synchronization flag comprising a bit of the address field of the PCI Configuration Address Port.

23. A Basic Input/Output System (BIOS) of a computer system with a PCI bus comprising instructions that when executed by the computer system, cause it to perform the method of claim 8.

24. The BIOS of claim 22 further comprising instructions that when executed by the computer system, cause it to perform the method of claim 10.

25. The BIOS of claim 24 further comprising instructions that when executed by the computer system, cause it to perform the method of claim 11.

13. An apparatus comprising:

a register normally dedicated to store and access a configuration parameter;

an indicator to indicate whether the register is available for configuration use;

a first processor capable of accessing the register, the processor to toggle the indicator to indicate that the register is unavailable for configuration use and

to store data other than the configuration parameter in the register;

a second processor to access data from the register; and

at least one of the first processor and the second processor, to toggle the indicator to indicate that the register is available for configuration use after the data has been accessed.

14. The apparatus of claim 13 wherein

the register is an address register normally dedicated to storage of and access to an address of a device on a bus;

the first processor is a first processor in a multiprocessor system;

the second processor is a second processor in the multiprocessor system;

the indicator comprises a bit of the address register in which is stored either;

a first value to indicate that the register is available for addressing use;

or

a second value distinct from the first value to indicate that the register is unavailable for addressing use.

15. An multiprocessor system with a device access bus using an address register with an enable bit comprising:

a first processor to set the enable bit to a first value indicating that the bus is disabled and to store data other than a device address in the address register;

a second processor to access the data from the address register;

at least one of the first processor and the second processor to set the enable bit to a second value distinct from the first value after the data has been accessed to indicate that the bus is enabled.

16. The multiprocessor system of claim 15 wherein the device bus is a Peripheral Component Interconnect (PCI) bus, the address register is the PCI Configuration Address Port and the enable bit is the Enable bit of the PCI Configuration Address Port.