Architecture for controlling dissipated power in a system-on-chip and related system
First Claim
1. A system-on-chip (SoC) architecture including a plurality of blocks (12;
- M1, M2, . . . , Mn;
S1, S2, . . . , Sk), each block including a power control module (20) to selectively control the power dissipated by the block, characterized in that it includes a respective power control register (PCR) associated to each block of said plurality of blocks (12;
M1, M2, . . . , Mn;
S1, S2, . . . , Sk), said power control register (PCR) to receive power control instructions to selectively control the power control module (20) of the associated block (12;
M1, M2, . . . , Mn;
S1, S2, Sk), and at least one power control unit (16) for writing respective power control instructions into the power control registers (PCR) of the blocks of said plurality (12;
M1, M2, . . . , Mn;
S1, S2, . . . , Sk) whereby the power dissipated by said blocks is controlled individually and independently for each block of said plurality under the centralized control of said at least one power control unit (16).
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Abstract
A system-on-chip (SoC) architecture includes a plurality of blocks, each including a power control module to selectively control the power dissipated by the bloc. For each block, a power register is provided to receive power control instructions to selectively control the respective power control module. The system also includes a power control unit for writing respective power control instructions into the power control registers of the blocks, whereby the power dissipated is controlled individually and independently for each block under the centralized control of the power control unit. For each block, a power status register is also provided to receive status information concerning power control within the respective block. The power control unit reads the status instructions from such power status registers.
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Citations
10 Claims
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1. A system-on-chip (SoC) architecture including a plurality of blocks (12;
- M1, M2, . . . , Mn;
S1, S2, . . . , Sk), each block including a power control module (20) to selectively control the power dissipated by the block, characterized in that it includes a respective power control register (PCR) associated to each block of said plurality of blocks (12;
M1, M2, . . . , Mn;
S1, S2, . . . , Sk), said power control register (PCR) to receive power control instructions to selectively control the power control module (20) of the associated block (12;
M1, M2, . . . , Mn;
S1, S2, Sk), and at least one power control unit (16) for writing respective power control instructions into the power control registers (PCR) of the blocks of said plurality (12;
M1, M2, . . . , Mn;
S1, S2, . . . , Sk) whereby the power dissipated by said blocks is controlled individually and independently for each block of said plurality under the centralized control of said at least one power control unit (16). - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
- M1, M2, . . . , Mn;
Specification