Architecture for controlling dissipated power in a system-on-chip and related system

• US 20040019814A1
• Filed: 05/16/2003
• Published: 01/29/2004
• Est. Priority Date: 05/17/2002
• Status: Active Grant

• Current Assignee: Eridanus Technologies, Inc. (Wi-LAN Inc.)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV), STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Pappalardo, Francesco, Mantellassi, Luigi
• Granted Patent: US 7,178,044 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system-on-chip (SoC) architecture includes a plurality of blocks, each including a power control module to selectively control the power dissipated by the bloc. For each block, a power register is provided to receive power control instructions to selectively control the respective power control module. The system also includes a power control unit for writing respective power control instructions into the power control registers of the blocks, whereby the power dissipated is controlled individually and independently for each block under the centralized control of the power control unit. For each block, a power status register is also provided to receive status information concerning power control within the respective block. The power control unit reads the status instructions from such power status registers.

Claims

1. A system-on-chip (SoC) architecture including a plurality of blocks (12;

M1, M2, . . . , Mn;

S1, S2, . . . , Sk), each block including a power control module (20) to selectively control the power dissipated by the block, characterized in that it includes a respective power control register (PCR) associated to each block of said plurality of blocks (12;

M1, M2, . . . , Mn;

S1, S2, . . . , Sk), said power control register (PCR) to receive power control instructions to selectively control the power control module (20) of the associated block (12;

M1, M2, . . . , Mn;

S1, S2, Sk), and at least one power control unit (16) for writing respective power control instructions into the power control registers (PCR) of the blocks of said plurality (12;

M1, M2, . . . , Mn;

S1, S2, . . . , Sk) whereby the power dissipated by said blocks is controlled individually and independently for each block of said plurality under the centralized control of said at least one power control unit (16).

2. The architecture of claim 1, characterized in that it includes, for each block of said plurality (12;

M1, M2, . . . , Mn;

S1, S2, . . . , Sk), a power status register (PSR) to receive status information concerning power control within the respective block and in that said at least one power control unit (16) is arranged to a read said status instructions from said power status registers (PSR) of the blocks of said plurality.

3. The architecture of either of claims 1 or 2, characterized in that said at least one power control unit is a separate block (16) in the architecture.

4. The architecture of either of claims 1 or 2, characterized in that said plurality of blocks includes at least one master block (M1, M2, . . . , Mn) configured for writing respective power control instructions into said power control registers (PCR) of the blocks of said plurality.

5. The architecture of claim 2, characterized in that said plurality of blocks includes at least one master block (M1, M2, . . . , Mn) configured for reading said status instructions from said power status registers (PSR) of the blocks of said plurality.

6. The architecture of any of the previous claims, including a main bus (BUS1) to exchange information between the blocks of said plurality (12;

M1, M2, . . . , Mn;

S1, S2, Sk) and in that said power control instructions are distributed from said at least one power control unit (16) to the power control registers (PCR) of the blocks of said plurality (12;

M1, M2, . . . , Mn;

S1, S2, . . . , Sk) over said main bus (BUS1).

7. The architecture of claim 2 and claim 5, characterized in that said status instructions are sent from the power status registers (PSR) of the blocks of said plurality towards said at least one power control unit (16) over said main bus (BUS1).

8. The architecture of any of claims 1 to 5, characterized in that it includes a dedicated bus (18) for distributing said power control instructions from said at least one power control unit (16) towards the power control registers (PCR) of the blocks of said plurality (12;

M1, M2, . . . , Mn;

S1, S2, . . . , Sk).

9. The architecture of claim 2 and claim 8, characterized in that said status instructions are sent from the power status registers (PSR) of the blocks of said plurality towards said at least one power control unit (16) over said dedicated bus (18).

10. A system-on-chip (SOC) embodying the architecture of any of claims 1 to 9.