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Architecture for controlling dissipated power in a system-on-chip and related system

  • US 20040019814A1
  • Filed: 05/16/2003
  • Published: 01/29/2004
  • Est. Priority Date: 05/17/2002
  • Status: Active Grant
First Claim
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1. A system-on-chip (SoC) architecture including a plurality of blocks (12;

  • M1, M2, . . . , Mn;

    S1, S2, . . . , Sk), each block including a power control module (20) to selectively control the power dissipated by the block, characterized in that it includes a respective power control register (PCR) associated to each block of said plurality of blocks (12;

    M1, M2, . . . , Mn;

    S1, S2, . . . , Sk), said power control register (PCR) to receive power control instructions to selectively control the power control module (20) of the associated block (12;

    M1, M2, . . . , Mn;

    S1, S2, Sk), and at least one power control unit (16) for writing respective power control instructions into the power control registers (PCR) of the blocks of said plurality (12;

    M1, M2, . . . , Mn;

    S1, S2, . . . , Sk) whereby the power dissipated by said blocks is controlled individually and independently for each block of said plurality under the centralized control of said at least one power control unit (16).

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