Method and apparatus for efficient register-transfer level (RTL) power estimation

• US 20040019859A1
• Filed: 07/29/2002
• Published: 01/29/2004
• Est. Priority Date: 07/29/2002
• Status: Active Grant

• Current Assignee: NEC Corporation
• Original Assignee: NEC USA (NEC Corporation)
• Inventors: Raghunathan, Anand, Ravi, Srivaths, Chakradhar, Srimat T.
• Granted Patent: US 7,134,100 B2
• Time in Patent Office: Days
• US Class Current: 716/4
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

Techniques for accelerating power estimation for a circuit comprising generating an RTL description of the circuit. A power model enhanced RTL description of the circuit is generated. A simulator is selected. The power model enhanced RTL description is modified to make it more friendly to the simulator. The simulator is run to estimate the power consumed by the circuit. Techniques using delayed computation and partitioned sampling are also provided. Power estimation systems using the above techniques area also provided.

Claims

1. A method for accelerating power estimation for a circuit comprising:

generating an RTL description of the circuit;

generating a power model enhanced RTL description of the circuit;

selecting a simulator;

modifying the power model enhanced RTL description to make it more friendly to the simulator; and

running the simulator to estimate the power consumed by the circuit.

2. The method of claim 1, wherein the power model enhanced RTL description is modified by optimizing HDL semantics such that simulation performance is improved.

3. The method of claim 2, wherein the said optimizing is done by converting a data type of at least one operand involved in power model computations from a first data type to a second data type, wherein the second data type is simpler than the first data type.

4. The method of claim 2, wherein the said optimizing is done by expanding at least one HDL function so that the overheads of entering and exiting the function are removed.

5. The method of claim 2, wherein the said optimizing is done by shutting down an HDL description of at least one power model and activating said HDL description of the power model only when necessary.

6. The method of claim 2, wherein the said optimizing is done by reducing the workload of at least one power model.

7. The method of claim 6, wherein one-shot computations in the HDL code of the power model are moved to the exterior of power model, so that redundant evaluations are removed.

8. The method of claim 6, wherein computations inside a loop within the HDL code of the power model are moved to the exterior of the loop.

9. A method for accelerating power estimation for a circuit comprising:

generating an RTL description of the circuit;

generating a power model enhanced RTL description of the circuit;

selecting a simulator;

studying tradeoff issues between computation and memory usage for simulating the power model enhanced RTL description on the selected simulator;

reducing the required computation for simulating the power model enhanced RTL circuit description on the simulator by increasing memory usage; and

running the simulator to estimate the power consumed by the circuit.

10. The method of claim 9, wherein input and output values of RTL components are queued in each cycle and a compute operation for power consumption is performed only once in every k cycles, where k is a positive integer greater than 1.

11. A method for accelerating power estimation for a circuit comprising:

generating an RTL description of the circuit;

generating a power model enhanced RTL description;

selecting a simulator;

performing partitioning, wherein the RTL description is partitioned into clusters according to their power consumption profile;

deriving a customized sampling for each of said clusters; and

simulating the RTL description on the simulator based on the samplings.

12. The method of claim 11 wherein the partitioned sampling is performed by a process comprising:

i) computing a mean and a variance of power distribution for all RTL components in the power model enhanced RTL description.

ii) generating a mean-variance scatter plot;

iii) partitioning the RTL description based on the scatter plot to generate clusters of components with similar power characteristics;

iv) determining the sampling probability of each of the said clusters;

v) incorporating the clusters into the power model enhanced RTL description.

13. The method of claim 12 wherein computing the mean and variance of power distribution is performed by:

i) performing a short simulation run of the power model enhanced RTL description, wherein a short simulation is shorter than an overall simulation run;

ii) generating a power profile based on the short simulation run;

iii) computing the mean and variance of power from the power profile.

14. The method of claim 12, wherein partitioning is performed by a process comprising

A) computing a distance metric for measuring the similarities in the power profiles for every possible pair of RTL components;

wherein the distance is computed based on data that comprises the mean and variance of the power profiles for the corresponding RTL components;

B) generating an initial set of clusters and forming a cluster separation matrix (CSM) based on the computations in A;

C) computing average distance between every cluster pair in the CSM, wherein average distance between a cluster pair is calculated based on a distance between each component of a cluster and all components in another cluster;

D) merging two clusters with a lowest average distance and updating the CSM to reflect the merging;

E) repeating C-D until all components are in one cluster while recording the cluster merging sequence; and

F) using the cluster merging sequence to generate the final set of clusters.

15. The method of claim 12, wherein the said sampling probability is determined by minimizing the potential error due to the sampling.

16. The method of claim 14, wherein, during error computation, a first cluster that accounts for a greater fraction of power consumed is weighted more than a second cluster that accounts for a lesser fraction of the power consumed.

17. A power estimation system for power estimation for a circuit comprising:

a power model enhanced RTL description of the circuit;

a simulator; and

an RTL description modifier adapted to modify the power model enhanced RTL description to make it more friendly to the simulator.

18. The system of claim 17, wherein RTL description modifier is capable of modifying the power model enhanced RTL description by optimizing HDL semantics such that simulation performance is improved.

19. The system of claim 18, wherein the RTL description modifier is capable of optimizing by converting a data type of at least one operand involved in power model computations from a first data type to a second data type, wherein the second data type is simpler than the first data type.

20. The system of claim 18, wherein the RTL description modifier is capable of optimizing by expanding at least one HDL function so that the overheads of entering and exiting the function are removed.

21. The system of claim 18, wherein the RTL description modifier is capable of optimizing by shutting down an HDL description of at least one power model and activating said HDL description of the power model only when necessary.

22. The system of claim 18, wherein the RTL description modifier is capable of optimizing by reducing the workload of at least one power model.

23. The system of claim 18, wherein one-shot computations in the HDL code of at least one power model are moved to the exterior of the power model, so that redundant evaluations are removed.

24. The system of claim 23, wherein computations inside a loop within the HDL code of at least one power model are moved to the exterior of the loop.

25. A power estimation system for estimating power consumption of the circuit comprising:

a power enhanced RTL description of the circuit;

a simulator;

a partitioner capable of partitioning the RTL description is partitioned into clusters according to their power consumption profile;

a sample generator capable of deriving a customized sampling for each of said clusters,

wherein the simulator is capable of performing simulations using the customized samples.

26. A power estimation system for estimating power consumption of the circuit comprising:

a power enhanced RTL description of the circuit;

a simulator;

a memory estimator capable of studying tradeoff issues between computation and memory usage for simulating the power model enhanced RTL description on the simulator;

wherein the system is capable of reducing the required computation for simulating the power model enhanced RTL circuit description on the simulator by increasing memory usage prior to unning the simulator to estimate the power consumed by the circuit.

27. The system of claim 26, wherein the system is capable of queueing the input and output values of RTL components in each cycle and further capable of performing a compute operation for power consumption only once in every k cycles, where k is a positive integer greater than 1.