SYSTEM, CIRCUIT AND METHOD PROVIDING A DYNAMIC RANGE PIXEL CELL WITH BLOOMING PROTECTION

• US 20040021058A1
• Filed: 07/30/2002
• Published: 02/05/2004
• Est. Priority Date: 07/30/2002
• Status: Active Grant

• Current Assignee: Intellectual Ventures II LLC (Intellectual Ventures LLC)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Ramaswami, Shrinath, Drowley, Clifford I.
• Granted Patent: US 6,777,662 B2
• Time in Patent Office: Days
• US Class Current: 250/208.1
• CPC Class Codes: H04N 25/575 with a response composed of multiple slopes
• CPC Class Codes: H04N 25/59 by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors

Abstract

An extended dynamic range pixel cell providing blooming protection is disclosed herein. By applying a timed varying signal to a shunt transistor in order to shunt excess charge generated by a photosensor in response to high intensity illumination, blooming protection can be provided. In particular configurations, blooming protection is provided not only during an integration period but also during a readout period when the pixel cell is generally most susceptible to blooming problems. The time varying voltage is also used to extend the dynamic range of the pixel cell thereby increasing the pixel cells usefulness in high contrast conditions, such as bright sunlight casting deep shadows, nighttime automotive applications, and the like.

Claims

1. A pixel cell comprising:

a reset transistor, said reset transistor including;

a control node to be coupled to a first control signal;

a second current electrode to be coupled to a voltage supply; and

a first current electrode coupled to a floating node;

a buffer transistor, said first current electrode follower transistor including;

a control node coupled to said floating node;

a second current electrode to be coupled to said voltage supply; and

a first current electrode coupled to a second current electrode of an output control transistor;

a transfer transistor, said transfer transistor including;

a control node to be coupled to a second control signal;

a second current electrode coupled to said floating node; and

a first current electrode to provide an input of a photosensor;

a shunt transistor, said shunt transistor including;

a control node to be coupled to a shunt control signal;

a second current electrode coupled to be coupled to said voltage supply; and

a first current electrode to be coupled to said input of said photosensor;

a photosensor, said photosensor including;

an input coupled to said first current electrode of said shunt transistor and to said first current electrode of said transfer transistor; and

an output coupled to a voltage return.

2. The pixel cell as in claim 1, further including an output control transistor, said output control transistor including:

a control node to be coupled to a readout control signal;

a second current electrode coupled to said first current electrode of said buffer transistor; and

a first current electrode to provide an output of said pixel cell.

3. The pixel cell as in claim 1, wherein said first control signal is a time-varying signal.

4. The pixel cell as in claim 1, wherein:

said first control signal places said reset transistor in a conduction state during a pre-charging period; and

said first control signal places said reset transistor in a non-conduction state after an integration period.

5. The pixel cell as in claim 1, wherein said second control signal places said transfer transistor in a conduction state during a pre-charging period.

6. The pixel cell as in claim 1, wherein said second control signal places said transfer transistor in a non-conduction state during an integration period.

7. The pixel cell as in claim 1, wherein:

said second control signal places said transfer transistor in a conduction state to allow transfer of charge from said photosensor to said floating node during a transfer period; and

said second control signal places said transfer transistor in a non-conduction state after said transfer period.

8. The pixel cell as in claim 1, wherein said shunt control signal is a time-varying signal.

9. The pixel cell as in claim 8, wherein said shunt control signal is decreased from a maximum value to a lesser value over an integration period.

10. The pixel cell as in claim 8, wherein said shunt control signal is varied in discrete steps.

11. The pixel cell as in claim 8, wherein said shunt control signal is varied smoothly.

12. The pixel cell as in claim 1, wherein said variable biasing signal places said shunt transistor in a conduction state during a readout period.

13. The pixel cell as in claim 1, wherein said photosensor is a photodiode.

14. The pixel cell as in claim 13, wherein said photodiode is a pinned photodiode.

15. The pixel cell as in claim 1, wherein said photosensor is a photogate.

16. A pixel cell comprising:

a reset transistor, said reset transistor including;

a control node to be coupled to a reset control signal;

a second current electrode to be coupled to a voltage supply; and

a first current electrode coupled to a floating node;

a buffer transistor, said first current electrode follower transistor including;

a control node coupled to said floating node;

a second current electrode to be coupled to said voltage supply; and

a first current electrode coupled to a second current electrode of an output control transistor;

a shunt transistor, said shunt transistor including;

a control node to be coupled to a shunt control signal;

a second current electrode coupled to a voltage source; and

a source to be coupled to an input of a photosensor;

a photosensor, said photosensor including;

an input coupled to said first current electrode of said shunt transistor and to said floating node; and

an output coupled to a voltage return.

17. The pixel cell as in claim 16, further including an output control transistor, said output control transistor including:

a control node to be coupled to a readout control signal;

a second current electrode coupled to said first current electrode of said buffer transistor; and

a first current electrode to provide an output of said pixel cell.

18. The pixel cell as in claim 16, wherein said first control signal is a time-varying signal.

19. The pixel cell as in claim 16, wherein said first control signal places said reset transistor in a conduction state during a pre-charging period.

20. The pixel cell as in claim 16, wherein said first control signal places said reset transistor in a non-conduction state during an integration period.

21. The pixel cell as in claim 16, wherein said first control signal biases said reset transistor in a subthreshold region during an integration period.

22. The pixel cell as in claim 16, wherein said shunt control signal is a time-varying signal.

23. The pixel cell as in claim 22, wherein said shunt control signal is decreased from a maximum value to a lesser value over an integration period.

24. The pixel cell as in claim 22, wherein said shunt control signal is varied in discrete steps.

25. The pixel cell as in claim 22, wherein said shunt control signal is varied smoothly.

26. The pixel cell as in claim 16, wherein said photosensor is a photodiode.

27. The pixel cell as in claim 26, wherein said photodiode is a pinned photodiode.

28. The pixel cell as in claim 16, wherein said photosensor is a photogate.

29. A pixel cell comprising:

a reset transistor to control an amount of charge stored at a storage node;

a buffer transistor to drive an output of said pixel cell;

a photosensor to supply charge to be stored in said storage node;

a transfer transistor to selectively isolate said photosensor from said storage node; and

a shunt transistor to provide blooming protection for said photosensor.

30. The pixel cell as in claim 29, wherein said reset transistor and said shunt transistor are the same transistor.

31. The pixel cell as in claim 29, further including an output control transistor to control an output of said pixel cell.

32. The pixel cell as in claim 29, wherein a conduction state of said reset transistor is controlled by a time-varying signal.

33. The pixel cell as in claim 29, wherein said reset transistor is operated in a sub-threshold state during an integration period.

34. The pixel cell as in claim 29, wherein:

said reset transistor is operated in a conduction state during a pre-charging period; and

said reset transistor is placed in a non-conduction state after an integration period.

35. The pixel cell as in claim 29, wherein said transfer transistor is operated in a conduction state during a pre-charging period.

36. The pixel cell as in claim 29, wherein said transfer transistor is operated in a non-conduction state during an integration period.

37. The pixel cell as in claim 29, wherein:

said transfer transistor is operated in a conduction state to allow transfer of charge from said photosensor to said floating node during a transfer period; and

said transfer transistor is placed in a non-conduction state after said transfer period.

38. The pixel cell as in claim 29, wherein:

said a conduction state of said shunt transistor is controlled by a shunt control signal; and

wherein said shunt control signal is a time-varying signal

39. The pixel cell as in claim 38, wherein said shunt control voltage is decreased from a maximum value to a lesser value over an integration period.

40. The pixel cell as in claim 38, wherein said shunt control signal is varied in discrete steps.

41. The pixel cell as in claim 38, wherein said shunt control signal is varied smoothly.

42. The pixel cell as in claim 29, wherein said shunt control signal places said shunt transistor in a conduction state during a readout period.

43. The pixel cell as in claim 29, wherein said photosensor is a photodiode.

44. The pixel cell as in claim 43, wherein said photodiode is a pinned photodiode.

45. The pixel cell as in claim 29, wherein said photosensor is a photogate.

46. An imaging system comprising:

an array of pixel cells having outputs coupled to a column select line, each of said pixel cells including;

a reset transistor to control an amount of charge stored at a storage node;

a buffer transistor to drive an output of said pixel cell;

a photosensor to supply charge to be stored in said storage node;

a transfer transistor to selectively isolate said photosensor from said storage node; and

a shunt transistor to provide blooming protection for said photosensor.

47. The imaging system as in claim 46, wherein said reset transistor and said shunt transistor are the same transistor.

48. The imaging system as in claim 46, wherein said pixel cells further include an output control transistor to control an output of said pixel cell.

49. The imaging system as in claim 46, wherein a conduction state of said reset transistor is controlled by a time-varying signal.

50. The imaging system as in claim 46, wherein said reset transistor is operated in a sub-threshold state during an integration period.

51. The imaging system as in claim 46, wherein:

said reset transistor is operated in a conduction state during a pre-charging period; and

said reset transistor is placed in a non-conduction state after an integration period.

52. The imaging system as in claim 46, wherein said transfer transistor is operated in a conduction state during a pre-charging period.

53. The imaging system as in claim 46, wherein said transfer transistor is operated in a non-conduction state during an integration period.

54. The imaging system as in claim 46, wherein:

said transfer transistor is operated in a conduction state to allow transfer of charge from said photosensor to said floating node during a transfer period; and

said transfer transistor is placed in a non-conduction state after said transfer period.

55. The imaging system as in claim 46, wherein:

said a conduction state of said shunt transistor is controlled by a shunt control signal; and

wherein said shunt control signal is a time-varying signal

56. The imaging system as in claim 55, wherein said shunt control voltage is decreased from a maximum value to a lesser value over an integration period.

57. The imaging system as in claim 55, wherein said shunt control signal is varied in discrete steps.

58. The imaging system as in claim 55, wherein said shunt control signal is varied smoothly.

59. The imaging system as in claim 46, wherein said shunt control signal places said shunt transistor in a conduction state during a readout period.

60. The imaging system as in claim 46, wherein said photosensor is a photodiode.

61. The imaging system as in claim 60, wherein said photodiode is a pinned photodiode.

62. The imaging system as in claim 46, wherein said photosensor is a photogate.

63. A method for providing blooming protection in a pixel cell, the method comprising the steps of:

pre-charging a storage node;

providing charge to be stored in the storage node using a photosensor;

limiting an amount of charge stored in the storage node by applying a variable bias voltage to a transistor coupled between the storage node and a voltage supply; and

shunting excess charge generated by the photosensor through a transistor coupled between the photosensor and the voltage supply.

64. The method as in claim 63, wherein the step of limiting an amount of charge stored in the storage mode includes operating a reset transistor in a subthreshold state during an integration period.

65. The method as in claim 63, wherein the step of limiting an amount of charge stored in the storage mode includes applying the variable bias voltage to a shunt transistor.

66. The method as in claim 65, wherein the variable bias voltage is decreased from a maximum value to a lesser value over an integration period.

67. The method as in claim 65, wherein the variable bias voltage is varied in discrete steps.

68. The method as in claim 65, wherein the variable bias voltage is varied smoothly.

69. The method as in claim 63, wherein the step of pre-charging includes:

operating a reset transistor in a conduction state during a pre-charging period; and

placing the reset transistor in a non-conduction state after an integration period.

70. The method as in claim 63, wherein the step of pre-charging includes operating a transfer transistor in a conduction state during a pre-charging period.

71. The method as in claim 63, wherein the step of pre-charging includes operating a transfer transistor in a non-conduction state during an integration period.

72. The method as in claim 63, wherein the step of providing charge to be stored includes:

operating a transfer transistor in a conduction state to allow transfer of charge from the photosensor to the floating node during a transfer period; and

placing the transfer transistor in a non-conduction state after the transfer period.

73. The method as in claim 63, wherein the step of shunting includes operating a shunt transistor in a conduction state during a readout period.

74. The method as in claim 63, wherein the photosensor is a photodiode.

75. The method as in claim 74, wherein the photodiode is a pinned photodiode.

76. The pixel cell as in claim 63, wherein the photosensor is a photogate.